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2. Processor Architecture
NII-PRG | 2018.04.18
2.7.2. Download and Execute Software
Downloading software refers to the ability to download executable code and data to
the processor's memory via the JTAG connection. After downloading software to
memory, the JTAG debug module can then exit debug mode and transfer execution to
the start of executable code.
2.7.3. Software Breakpoints
Software breakpoints allow you to set a breakpoint on instructions residing in RAM.
The software breakpoint mechanism writes a break instruction into executable code
stored in RAM. When the processor executes the break instruction, control is
transferred to the JTAG debug module.
2.7.4. Hardware Breakpoints
Hardware breakpoints allow you to set a breakpoint on instructions residing in
nonvolatile memory, such as flash memory. The hardware breakpoint mechanism
continuously monitors the processor's current instruction address. If the instruction
address matches the hardware breakpoint address, the JTAG debug module takes
control of the processor.
Hardware breakpoints are implemented using the JTAG debug module's hardware
trigger feature.
2.7.5. Hardware Triggers
Hardware triggers activate a debug action based on conditions on the instruction or
data bus during real-time program execution. Triggers can do more than halt
processor execution. For example, a trigger can be used to enable trace data
collection during real-time processor execution.
Hardware trigger conditions are based on either the instruction or data bus. Trigger
conditions on the same bus can be logically ANDed, enabling the JTAG debug module
to trigger, for example, only on write cycles to a specific address.
Table 5.
Trigger Conditions
Condition
Specific address
Specific data value
Read cycle
Write cycle
Armed
Range
When a trigger condition occurs during processor execution, the JTAG debug module
triggers an action, such as halting execution, or starting trace capture. The table
below lists the trigger actions supported by the Nios II JTAG debug module.
Bus
Data, Instruction
Trigger when the bus accesses a specific address.
Data
Trigger when a specific data value appears on the bus.
Data
Trigger on a read bus cycle.
Data
Trigger on a write bus cycle.
Data, Instruction
Trigger only after an armed trigger event. Refer to the Armed Triggers section.
Data
Trigger on a range of address values, data values, or both. Refer to the
Triggering on Ranges of Values section.
Description
Nios II Processor Reference Guide
33
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