Intel NIOS II Owner Reference Manual page 61

3. Programming Model
NII-PRG | 2018.04.18
Table 34. mpuacc Control Register Field Descriptions
Field
specifies the size of the region.
MASK MASK
specifies the upper address limit of the region.
LIMIT LIMIT
( ) Memory Type:
MT MT
• 0 = peripheral (non-cacheable, non-write bufferable)
• 1 = normal (cacheable, write bufferable)
• 2 = device (non-cacheable, write bufferable)
• 3 = reserved
specifies the access permissions for the region.
PERM PERM
is the read region flag. When
RD RD
mpuacc
is the write region flag. When
WR WR
mpuacc
The
MASK
Field for MASK Variation Table and mpuacc Control Register Field for LIMIT Variation
Table.
The following sections provide more information about the
Related Information
• The LIMIT Field
• The MASK Field
3.4.2.14.1. The MASK Field
When the amount of memory reserved for a region is defined by size, the
specifies the size of the memory region. The
the
BASE
Note: Unused high-order or low-order bits must be written as zero and are read as zero.
MASK Region Size Encodings Table lists the
sizes in a full 31-bit byte address space.
(12)
This field size is variable. Unused upper bits and unused lower bits must be written as zero.
Description
= 1,
RD
register perform a read operation.
= 1,
WR
register perform a write operation.
and fields are mutually exclusive. Refer to mpucc Control Register
LIMIT
on page 62
on page 61
field of the register.
mpubase
instructions to the
wrctl
instructions to the
wrctl
field is the same number of bits as
MASK
field encodings for all possible region
MASK
Access Reset Availabl
Read/Write 0 Only
with
MPU
Read/Write 0 Only
with
MPU
Read/Write 0 Only
with
MPU
Read/Write 0 Only
with
MPU
Write 0 Only
with
MPU
Write 0 Only
with
MPU
fields.
mpuacc
field
MASK
Nios II Processor Reference Guide
e
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