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5. Nios II Core Implementation Details
NII-PRG | 2018.04.18
5.4.1. Overview
The Nios II/e core:
•
Executes at most one instruction per six clock cycles
•
Full 32-bit addressing
•
Can access up to 4 GB of external address space
•
Supports the addition of custom instructions
•
Supports the JTAG debug module
•
Does not provide hardware support for potential unimplemented instructions
•
Has no instruction cache or data cache
•
Does not perform branch prediction
The following sections discuss the noteworthy details of the Nios II/e core
implementation. This document does not discuss low-level design issues, or
implementation details that do not affect Nios II hardware or software designers.
5.4.2. Arithmetic Logic Unit
The Nios II/e core does not provide hardware support for any of the potential
unimplemented instructions. All unimplemented instructions are emulated in software.
The Nios II/e core employs dedicated shift circuitry to perform shift and rotate
operations. The dedicated shift circuitry achieves one-bit-per-cycle shift and rotate
operations.
5.4.3. Memory Access
The Nios II/e core does not provide instruction cache or data cache. All memory and
peripheral accesses generate an Avalon-MM transfer. The Nios II/e core can address
up to 4 GB of external memory, full 32-bit addressing.
For information regarding data cache bypass methods, refer to the Processor
Architecture chapter of the Nios II Processor Reference Handbook.
The Nios II/e core does not provide instruction cache or data cache. All memory and
peripheral accesses generate an Avalon-MM transfer.
For information regarding data cache bypass methods, refer to the Processor
Architecture chapter of the Nios II Processor Reference Handbook.
Related Information
Processor Architecture
5.4.4. Instruction Execution Stages
This section provides an overview of the pipeline behavior as a means of estimating
assembly execution time. Most application programmers never need to analyze the
performance of individual instructions.
on page 14
Nios II Processor Reference Guide
141
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