Vectors Tab; Reset Vector - Intel NIOS II Owner Reference Manual

4. Instantiating the Nios II Processor
NII-PRG | 2018.04.18
Intel FPGA offers the following Nios II cores:
• Nios II/f—The Nios II/f fast core is designed for fast performance. As a result,
this core presents the most configuration options allowing you to fine tune the
processor for performance.
• Nios II/e—The Nios II/e economy core is designed to achieve the smallest
possible core size. As a result, this core has a limited feature set, and many
settings are not available when the Nios II/e core is selected.
The Main tab displays a selector guide table that lists the basic properties of each
core.
For implementation information about each core, refer to the Nios II Core
Implementation Details chapter of the Nios II Processor Reference Handbook.
Related Information
Nios II Core Implementation Details

4.2. Vectors Tab

Figure 7. Nios II Platform Designer Vector Tab

4.2.1. Reset Vector

Parameters in this section select the memory module where the reset code (boot
loader) resides, and the location of the reset vector (reset address). The reset vector
cannot be configured until your system memory components are in place.
The Reset vector memory list, which includes all memory modules mastered by the
Nios II processor, selects the reset vector memory module. In a typical system, select
a nonvolatile memory module for the reset code.
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Nios II Processor Reference Guide
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