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  • Page 1 Nios II Processor Reference Guide Subscribe NII-PRG | 2018.04.18 Send Feedback Latest document on the web: HTML...

  • Page 2: Table Of Contents

    2.2. Register File......................16 2.3. Arithmetic Logic Unit.................... 17 2.3.1. Unimplemented Instructions..............17 2.3.2. Custom Instructions................. 17 2.3.3. Introduction to Nios II Floating Point Custom Instructions......18 2.4. Reset and Debug Signals..................21 2.5. Exception and Interrupt Controllers................ 22 2.5.1. Exception Controller................. 22 2.5.2.
  • Page 3 3.9.8. Custom Instructions................104 3.9.9. No-Operation Instruction.................105 3.9.10. Potential Unimplemented Instructions............. 105 3.10. Programming Model Revision History..............105 4. Instantiating the Nios II Processor................106 4.1. Main Nios II Tab....................106 4.2. Vectors Tab....................... 107 4.2.1. Reset Vector..................107 4.2.2. Exception Vector..................108...
  • Page 4 4.7.7. Exception Checking................119 4.7.8. Branch Prediction................... 120 4.7.9. RAM Memory Protection................120 4.8. The Quartus Prime IP File..................120 4.9. Instantiating the Nios II Processor Revision History..........120 5. Nios II Core Implementation Details................121 5.1. Device Family Support..................121 5.2. Nios II/f Core....................122 5.2.1.
  • Page 5 5.4.4. Instruction Execution Stages..............141 5.4.5. Instruction Performance................142 5.4.6. Exception Handling.................142 5.4.7. JTAG Debug Module................142 5.5. Nios II Core Implementation Details Revision History..........143 6. Nios II Processor Versions..................144 6.1. Nios II Versions....................144 6.2. Architecture Revisions..................144 6.3. Core Revisions....................145 6.3.1.
  • Page 6 8.5.40. cmpnei ....................194 8.5.41. custom ....................195 8.5.42. div ....................196 8.5.43. divu ....................197 8.5.44. eret ....................197 8.5.45. flushd ....................198 8.5.46. flushda ....................199 8.5.47. flushi ....................200 8.5.48. flushp ....................201 8.5.49. initd ....................201 Nios II Processor Reference Guide...
  • Page 7 8.5.91. subi ....................229 8.5.92. sync ....................229 8.5.93. trap ....................230 8.5.94. wrctl ....................230 8.5.95. wrprs ....................231 8.5.96. xor ....................232 8.5.97. xorhi ....................232 8.5.98. xori ....................233 8.6. Instruction Set Reference Revision History.............233 Nios II Processor Reference Guide...

  • Page 8: Introduction

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 9: Getting Started With The Nios Ii Processor

    A Nios II processor system consists of a Nios II processor core, a set of on-chip peripherals, on-chip memory, and interfaces to off-chip memory, all implemented on a single Intel FPGA device.

  • Page 10: Customizing Nios Ii Processor Designs

    If the prototype system adequately meets design requirements using an Intel- provided reference design, you can copy the reference design and use it without modification in the final hardware platform. Otherwise, you can customize the Nios II processor system until it meets cost or performance requirements.

  • Page 11: Configurable Soft Processor Core Concepts

    1.4.1. Configurable Soft Processor Core The Nios II processor is a configurable soft IP core, as opposed to a fixed, off-the-shelf microcontroller. You can add or remove features on a system-by-system basis to meet performance or price goals.

  • Page 12: Automated System Generation

    The custom logic is integrated into the Nios II processor’s arithmetic logic unit (ALU). Similar to native Nios II instructions, custom instruction logic can take values from up to two source registers and optionally write back a result to a destination register.

  • Page 13: Intel Fpga Ip Evaluation Mode

    • Program a device and verify your design in hardware. You only need to purchase a license for the Nios II processor when you are completely satisfied with its functionality and performance, and want to take your design to production.

  • Page 14: Processor Architecture

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 15: Processor Implementation

    A functional unit can be implemented in hardware, emulated in software, or omitted entirely. A Nios II implementation is a set of design choices embodied by a particular Nios II processor core. All implementations support the instruction set defined in the Instruction Set Reference chapter.

  • Page 16: Register File

    For information about which Nios II cores supports what features, refer to the Nios II Core Implementation Details chapter of the Nios II Processor Reference Handbook. For complete details about user-selectable parameters for the Nios II processor, refer to the Instantiating the Nios II Processor chapter of the Nios II Processor Reference Handbook.

  • Page 17: Arithmetic Logic Unit

    Refer to "Custom Instruction Tab" in the Instantiating the Nios II Processor chapter of the Nios II Processor Reference Handbook for additional information.

  • Page 18: Introduction To Nios Ii Floating Point Custom Instructions

    106 • Nios II Custom Instruction User Guide 2.3.3. Introduction to Nios II Floating Point Custom Instructions The Nios II architecture supports single precision floating point instructions with either of two optional components: • Floating point hardware 2 (FPH2)—This component supports floating point...
  • Page 19 The maximum error of faithful rounding is 1 unit in the last place (ulp). Errors may not be evenly distributed. This operation is not fully compliant with IEEE 754-2008. Nios II Processor Reference Guide...
  • Page 20 GCC does not support. Specifies the 8 bit fixed custom instruction for the operation. Nios II GCC version 4.7.3 is not able to reliably replace calls to newlib floating-point functions with the equivalent custom instruction even though it has Flush to 0 <operation>...

  • Page 21: Reset And Debug Signals

    The number of cycles does not include the extra cycles (maximum of 2) that an instruction following the multi-cycle custom instruction is stalled by the Nios II/f if the instruction uses the result within 2 cycles. These extra cycles occur because multi-cycle instructions are late result instructions In Platform Designer, the Floating Point Hardware 2 component is under Embedded Processors on the Component Library tab.

  • Page 22: Exception And Interrupt Controllers

    “Advanced Features Tab” in the Instantiating the Nios II Processor chapter of the Nios II Processor Reference Handbook. For more information on the break vector and adding debug signals to the Nios II processor, refer to “JTAG Debug Module Tab” in the Instantiating the Nios II Processor chapter of the Nios II Processor Reference Handbook.

  • Page 23: Eic Interface

    Note: When the EIC interface and shadow register sets are implemented on the Nios II core, you must ensure that your software is built with the Nios II EDS version 9.0 or higher. Earlier versions have an implementation of the...

  • Page 24: Memory And I/O Organization

    Nios II processor systems are configurable, the memories and peripherals vary from system to system. As a result, the memory and I/O organization varies from system to system. A Nios II core uses one or more of the following to provide memory and I/O access: ® ®...

  • Page 25: Instruction And Data Buses

    Note: The Nios II instruction and data masters have a combined address map. The memory model is arranged so that instructions and data are in the same address space. Related Information Avalon Interface Specifications Refer to the Avalon Interface Specifications for details of the Avalon-MM interface.
  • Page 26 2.6.1.1. Memory and Peripheral Access The Nios II architecture provides memory-mapped I/O access. Both data memory and peripherals are mapped into the address space of the data master port. The Nios II architecture uses little-endian byte ordering. Words and halfwords are stored in memory with the more-significant bytes at higher addresses.

  • Page 27: Cache Memory

    Nios II processor system might present a single, shared instruction/ data bus to the outside world. The outside view of the Nios II processor system depends on the memory and peripherals in the system and the structure of the system interconnect fabric.
  • Page 28 2. Processor Architecture NII-PRG | 2018.04.18 A Nios II processor core might include one, both, or neither of the cache memories. Furthermore, for cores that provide data and/or instruction cache, the sizes of the cache memories are user-configurable. The inclusion of cache memory does not affect the functionality of programs, but it does affect the speed at which the processor fetches instructions and reads/writes data.

  • Page 29: Tightly-Coupled Memory

    Physically, a tightly-coupled memory port is a separate master port on the Nios II processor core, similar to the instruction or data master port. A Nios II core can have zero, one, or multiple tightly-coupled memories. The Nios II architecture supports tightly-coupled memory for both instruction and data access.

  • Page 30: Address Map

    For additional tightly-coupled memory guidelines. 2.6.4. Address Map The address map for memories and peripherals in a Nios II processor system is design dependent. You specify the address map in Platform Designer. There are three addresses that are part of the processor and deserve special mention: •...

  • Page 31: Memory Protection Unit

    Handbook. Note: The Nios II MMU is optional and mutually exclusive from the Nios II MPU. Nios II systems can include either an MMU or MPU, but cannot include both an MMU and MPU on the same Nios II processor core.

  • Page 32: Jtag Debug Module

    In both cases, the processor transfers execution to the routine located at the break address. The break address is specified with the Nios II Processor parameter editor in Platform Designer.

  • Page 33: Download And Execute Software

    When a trigger condition occurs during processor execution, the JTAG debug module triggers an action, such as halting execution, or starting trace capture. The table below lists the trigger actions supported by the Nios II JTAG debug module. Nios II Processor Reference Guide...

  • Page 34: Trace Capture

    Certain trace features require additional licensing or debug tools from third-party debug providers. For example, an on-chip trace buffer is a standard feature of the Nios II processor, but using an off-chip trace buffer requires additional debug software ™ and hardware provided by Imagination Technologies , LLC or Lauterbach GmbH.

  • Page 35: Processor Architecture Revision History

    Therefore, while data frames are always stored in chronological order, execution and data trace are not guaranteed to be exactly synchronized with each other. 2.8. Processor Architecture Revision History Document Changes Version 2018.04.18 Implemented editorial enhancements. 2016.10.28 Maintenance release. 2015.04.02 Initial release Nios II Processor Reference Guide...

  • Page 36: Programming Model

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 37: User Mode

    3.2.1. Recommended Usage Including the Nios II MMU in your Nios II hardware system is optional. The MMU is only useful with an operating system that takes advantage of it. Nios II Processor Reference Guide...

  • Page 38: Memory Management

    (HAL) or a third party real-time operating system) is sufficient. Such software is unlikely to function correctly in a hardware system with an MMU-based Nios II processor. Do not include an MMU in your Nios II system unless your operating system requires it.

  • Page 39: Address Space And Memory Partitions

    Memory Protection The Nios II MMU maintains read, write, and execute permissions for each page. The TLB provides the permission information when translating a VPN. The operating system can control whether or not each process is allowed to read data from, write data to, or execute instructions on each particular page.
  • Page 40 When data cacheability is enabled on a partition of the address space, a data access to that partition can be cached, if a data cache is present in the system. When data cacheability is disabled, all access to that partition goes directly to Nios II Processor Reference Guide...

  • Page 41: Tlb Organization

    3.2.4. TLB Organization A TLB functions as a cache for the operating system’s page table. In Nios II processors with an MMU, one main TLB is shared by instruction and data accesses. The TLB is stored in on-chip RAM and handles translations for instruction fetches and instructions that perform data accesses.

  • Page 42: Tlb Lookups

    20 bits. is the cacheable flag. Determines the default data cacheability of a page. Can be overridden for data accesses using I/O load and store family of Nios II instructions. is the readable flag. Allows load instructions to read a page.

  • Page 43: Memory Protection Unit

    For information about memory protection with virtual memory management, refer to the Memory Management Unit section. When present and enabled, the MPU monitors all Nios II instruction fetches and data memory accesses to protect against errant software execution. The MPU is a hardware facility that system software uses to define memory regions and their associated access permissions.
  • Page 44 The maximum supported region size equals the Nios II address space (a function of the address ranges of slaves connected to the Nios II masters). Any access outside of the Nios II address space is considered not to match any region and triggers an MPU region violation exception.

  • Page 45: Overlapping Regions

    68 3.4. Registers The Nios II register set includes general-purpose registers and control registers. In addition, the Nios II/f core can optionally have shadow register sets. This section discusses each register type. 3.4.1. General-Purpose Registers The Nios II architecture provides thirty-two 32-bit general-purpose registers, through .

  • Page 46: Control Registers

    ) in each shadow register set. For details sstatus about , refer to The Status Register section. sstatus For more information, refer to the Application Binary Interface chapter of the Nios II Processor Reference Handbook. Related Information Application Binary Interface on page 146 3.4.2.
  • Page 47 Note: When writing to control registers, all undefined bits must be written as zero. The Nios II architecture supports up to 32 control registers. All nonreserved control registers have names recognized by the assembler. Nios II Processor Reference Guide...
  • Page 48 The following sections describe the nonreserved control registers. 3.4.2.1. The status Register The value in the register determines the state of the Nios II processor. All status bits are set to predefined values at processor reset. Some bits are exclusively...
  • Page 49 The number of significant bits in the fields depends on the number of shadow register sets implemented in the Nios II core. The value of can range from 0 to n-1, where n is the number of implemented register sets. The processor core implements the number of significant bits needed to represent n-1.
  • Page 50 All fields in the register have read/write access. All fields reset to 0. estatus When the Nios II processor takes an interrupt, if is zero (that is, the MMU status.eh is in nonexception mode), the processor copies the contents of the...
  • Page 51 Refer to the Exception Processing section for more information. Note: When the internal interrupt controller is not implemented, the value of the ienable register is always 0. Related Information Exception Processing on page 74 Nios II Processor Reference Guide...
  • Page 52 Note: The exception register is not available for Nios II/e core, therefore you cannot add a MMU or MPU to the processor configuration. For more information, refer to the Nios II Core Implementation Details chapter of this document.
  • Page 53 TLB tlbmisc.WE wrctl write operation, which writes a TLB entry. The TLB entry written is specified by the line portion of and the field. The value written is specified by pteaddr.VPN tlbmisc.WAY Nios II Processor Reference Guide...
  • Page 54 TLB write operation. 3.4.2.10. The tlbmisc Register register contains the remaining TLB-related fields and is only available tlbmisc in systems with an MMU. Table 24. tlbmisc Control Register Fields Bit Fields Reserved PERM Nios II Processor Reference Guide...
  • Page 55 TLB entry: • The tag portion of pteaddr.VPN • tlbmisc.PID • register tlbacc The TLB entry to be read is specified by the following values: • the line portion of pteaddr.VPN • tlbmisc.WAY Nios II Processor Reference Guide...
  • Page 56 TLB miss condition. When a general exception occurs, the MMU sets to one if a double TLB miss is detected, and clears to zero otherwise. Nios II Processor Reference Guide...
  • Page 57 Note: The exception register is not available for Nios II/e core, therefore you cannot add a MMU or MPU to the processor configuration. For more information, refer to the Nios II Core Implementation Details chapter of this document.
  • Page 58 If there is no MMU or MPU and the Nios II address space is less than 32 bits, unused high-order bits are written and read as zero. If there is no MMU, bit 31 of a data address (used to bypass the data cache) is always zero in the field.
  • Page 59 Only with ECC is the ECC error exception enable bit. When = 1, the ECCEXE ECCEX ECCEXE Nios II processor generates ECC error exceptions. Read/Write Only with ECC is the ECC enable bit. When = 0, the Nios II processor ECCEN...
  • Page 60 1024 bytes, the four least-significant bits of the field BASE (bits 6 though 9 of the register) must be zero. Similarly, if the Nios II mpubase address space is less than 31 bits, unused high-order bits must also be written as zero and are read as zero.
  • Page 61 MASK Region Size Encodings Table lists the field encodings for all possible region MASK sizes in a full 31-bit byte address space. (12) This field size is variable. Unused upper bits and unused lower bits must be written as zero. Nios II Processor Reference Guide...
  • Page 62 0x50 0x5000 >> 8 field is one more bit than the number of bits of the field of the LIMIT BASE mpubase register, bit 31 of the register is available to the field. mpuacc LIMIT Nios II Processor Reference Guide...
  • Page 63 The encoding of the MT field is setup to be backwards-compatible with the Nios II Classic core MPU where bit 5 of MPUACC contains the cacheable bit (0 = non- cacheable, 1 = cacheable) and bit 6 is zero.
  • Page 64 MPU Region Read and Write Operations on page 68 3.4.2.14.7. The eccinj Register register injects 1 and 2 bit errors to the Nios II processor’s internal RAM eccinj blocks that support ECC. Injecting errors allows the software to test the ECC error exception handling code.

  • Page 65: Shadow Register Sets

    A Nios II core can have up to 63 shadow register sets. If n is the configured number of shadow register sets, the shadow register sets are numbered from 1 to n. Register set 0 is the normal register set.
  • Page 66 3. Programming Model NII-PRG | 2018.04.18 3.4.3.1. The sstatus Register The value in the register preserves the state of the Nios II processor during sstatus external interrupt handling. The value of is undefined at processor reset. sstatus Some bits are exclusively used by and available only to certain features of the processor.
  • Page 67 There is one copy of for each shadow sstatus register set. When the Nios II processor takes an interrupt, if a shadow register set is requested (RRS = 0) and the MMU is not in exception handler mode ( = 0), the status.EH...

  • Page 68: Working With The Mpu

    However, instructions to the control registers wrctl mpubase mpuacc do not automatically flush the pipeline. Instead, system software is responsible for Nios II Processor Reference Guide...

  • Page 69: Mpu Initialization

    During debugging, the Nios II ignores the MPU, effectively rdctl temporarily disabling it. 3.6. Working with ECC 3.6.1. Enabling ECC The ECC is disabled on system reset. Before enabling the ECC, initialize the Nios II RAM blocks to avoid spurious ECC errors. Nios II Processor Reference Guide...

  • Page 70: Handling Ecc Errors

    WRPRS Nios II processor instructions that write every TLB RAM location initialize the MMU TLB RAM. This RAM does not require special initialization. 3.6.1.1. Disabling ECC Disable ECC in software by writing 0 to .
  • Page 71 (first to inject the ECC error and second to be triggered by it). 3.6.3.3. ITCMs Software running on the Nios II cannot directly inject an ECC error in an ITCM because the Nios II only writes s when correcting ECC errors. To inject an ECC in...
  • Page 72 LOAD 2. Use a instruction to set field to (as desired). WRCTL ECCINJ.DCDAT INJS INJD 3. Use a instruction to an address in the data cache line. STORE Nios II Processor Reference Guide...
  • Page 73 TLB entry. The ECC error will be injected at this WRCTL time and any associated uTLB entry will be flushed. 3. Use a instruction to ensure the value of RDCTL ECCINJ.TLB NOINJ Nios II Processor Reference Guide...

  • Page 74: Exception Processing

    • Internal interrupt controller—the nonvectored interrupt controller that is integral to the Nios II processor. The internal interrupt controller is available in all revisions of the Nios II processor. • Vectored interrupt controller (VIC)—an Intel-provided external interrupt controller.

  • Page 75: Exception Overview

    • Reset exception—Occurs when the Nios II processor is reset. Control is transferred to the reset address you specify in the Nios II processor IP core setup parameters. • Break exception—Occurs when the JTAG debug module requests control. Control is transferred to the break address you specify in the Nios II processor IP core setup parameters.
  • Page 76 MMU and ECC General (data badaddr related exception address) (16) Division error Instruction- Division error detection General ea–4 related exception Fast TLB miss (data) Instruction- Fast TLB pteaddr.VPN related Miss (data badaddr exception address) continued... Nios II Processor Reference Guide...

  • Page 77: Exception Latency

    3.7.4. Reset Exceptions When a processor reset signal is asserted, the Nios II processor performs the following steps: 1. Sets to 1, and clears all other fields of the register.

  • Page 78: Break Exceptions

    • Custom instruction logic • Nios II C-to-hardware (C2H) acceleration compiler logic. For more information refer to the Nios II Custom Instruction User Guide for reset conditions. Related Information Nios II Custom Instruction User Guide 3.7.5. Break Exceptions A break is a transfer of control away from a program’s normal flow of execution for the...

  • Page 79: Interrupt Exceptions

    A peripheral device can request an interrupt by asserting an interrupt request (IRQ) signal. IRQs interface to the Nios II processor through an interrupt controller. You can configure the Nios II processor with either of the following interrupt controller options:...
  • Page 80 Requested nonmaskable interrupt (RNMI) mode—Refer to the Requested NMI Mode section of this chapter The Nios II processor EIC interface connects to a single EIC, but an EIC can support a daisy-chained configuration. In a daisy-chained configuration, multiple EICs can monitor and prioritize interrupts.
  • Page 81 If the Nios II processor is implemented with an MMU, the processor treats handler addresses as virtual addresses. 3.7.6.1.2. Requested Interrupt Level The Nios II processor uses the RIL to decide when to take a maskable interrupt. The interrupt is taken only when the RIL is greater than status.IL The RIL is ignored for nonmaskable interrupts.
  • Page 82 81 3.7.6.2. Internal Interrupt Controller When the internal interrupt controller is implemented, a peripheral device can request a hardware interrupt by asserting one of the Nios II processor’s 32 interrupt-request inputs, through . A hardware interrupt is generated if and only if all three...

  • Page 83: Instruction-Related Exceptions

    Exception Processing Flow on page 88 3.7.7. Instruction-Related Exceptions Instruction-related exceptions occur during execution of Nios II instructions. When they occur, the processor perform the steps outlined in the "Exception Processing Flow" section of this chapter. The Nios II processor generates the following instruction-related exceptions: •...
  • Page 84 3.7.7.4. Illegal Instruction Illegal instructions are instructions with an undefined opcode or opcode-extension field. The Nios II processor can check for illegal instructions and generate an exception when an illegal instruction is encountered. Illegal instruction checking is always on regardless of MMU or MPU settings.
  • Page 85 Executing one of these undefined opcodes does not trigger an illegal instruction exception. Refer to the Nios II Core Implementation Details chapter of the Nios II Processor Reference Handbook for information about each specific Nios II core.
  • Page 86 Related Information Programming Model on page 36 3.7.7.10. Division Error The Nios II processor can check for division errors and generate an exception when a division error is encountered. Nios II Processor Reference Guide...
  • Page 87 36 3.7.7.11. Fast TLB Miss Fast TLB miss exceptions are implemented only in Nios II processors that include the MMU. The MMU has a special exception vector (fast TLB miss), specified with the Nios II Processor parameter editor in Platform Designer, specifically to handle TLB miss exceptions quickly.

  • Page 88: Other Exceptions

    MPU region violation exception occurred. 3.7.8. Other Exceptions The preceding sections describe all of the exception types defined by the Nios II architecture at the time of publishing. However, some processor implementations might generate exceptions that do not fall into the categories listed in the preceding sections.
  • Page 89 RNMI—The requested NMI flag specifies whether to treat the interrupt as nonmaskable. For further information about the RHA, RRS, RIL and RNMI, refer to “The Nios II/f Core” in the Nios II Core Implementation Details chapter of the Nios II Processor Reference Handbook.
  • Page 90 3. Programming Model NII-PRG | 2018.04.18 When the EIC interface presents an interrupt to the Nios II processor, the processor uses several criteria, as follows, to determine whether to take the interrupt: • Nonmaskable interrupts—The processor takes any NMI as long as it is not processing a previous NMI.
  • Page 91 No change continued... (19) If the Nios II processor does not have an EIC interface, external interrupts do not occur. (20) If the Nios II processor does not have an MMU, this register is not implemented. (21) The VPN of the address triggering the exception...
  • Page 92 (32) If the MMU is implemented, indicates that the processor is handling an exception. (33) Puts the processor in supervisor mode. (34) If the Nios II processor does not have an MMU, this field is not implemented. Its value is always 0, and the processor behaves accordingly. (35) If the Nios II processor does not have shadow register sets, this field is not implemented.

  • Page 93: Determining The Cause Of Interrupt And Instruction-Related Exceptions

    BADDR badaddr byte instruction address or data address for certain exceptions. Refer to the Nios II Exceptions table for more information in the Exception Overview section. Note: External interrupts do not set exception CAUSE To determine the cause of an exception, simply read the cause of the exception from and then transfer control to the appropriate exception routine.

  • Page 94: Handling Nested Exceptions

    • An exception handler triggers an instruction-related exception For details about when the Nios II processor takes exceptions, refer to “Exception Processing Flow” on page 3–44. For details about unimplemented instructions, refer to the Processor Architecture chapter of the Nios II Processor Reference Handbook.
  • Page 95 3. Programming Model NII-PRG | 2018.04.18 When individual external interrupts have dedicated shadow register sets, the Nios II processor supports fast interrupt handling with no overhead for saving register contents. To take full advantage of fast interrupt handling, system software must set up certain conditions.

  • Page 96: Handling Nonmaskable Interrupts

    NMI mode until the next nonmaskable interrupt. 3.7.13. Masking and Disabling Exceptions The Nios II processor provides several methods for temporarily turning off some or all exceptions from software. The available methods depend on the hardware configuration. This section discusses all potentially available methods.
  • Page 97 In the case of ISRs, if the EIC interface and shadow register sets are implemented, and the ISR has a dedicated register set, no software action is required. The Nios II processor returns to the previous register set when it executes , which restores the register contents.

  • Page 98: Memory And Peripheral Access

    NMI mode. Note: When the EIC interface and shadow register sets are implemented on the Nios II core, you must ensure that your software, including ISRs, is built with the version of the GCC compiler included in Nios II EDS version 9.0 or later.

  • Page 99: Cache Memory

    Cache bypass instructions, such as ldwio stwio Refer to the Nios II Core Implementation Details chapter of the Nios II Processor Reference Handbook for details of which processor cores implement bit-31 cache bypass. Refer to Instruction Set Reference chapter of the Nios II Processor Reference Handbook for details of the cache bypass instructions.

  • Page 100: Instruction Set Categories

    PFN. 3.9. Instruction Set Categories This section introduces the Nios II instructions categorized by type of operation performed. 3.9.1. Data Transfer Instructions The Nios II architecture is a load-store architecture.

  • Page 101: Arithmetic And Logical Instructions

    This instruction is used in computing a 128-bit result of a 64x64 signed multiplication. mulxsu 3.9.3. Move Instructions These instructions provide move operations to copy the value of a register or an immediate value to another register. Nios II Processor Reference Guide...

  • Page 102: Comparison Instructions

    3.9.4. Comparison Instructions The Nios II architecture supports a number of comparison instructions. All of these compare two registers or a register and an immediate value, and write either one (if true) or zero to the result register. These instructions perform all the equality and relational operators of the C programming language.

  • Page 103: Program Control Instructions

    3.9.6. Program Control Instructions The Nios II architecture supports the unconditional jump, branch, and call instructions. These instructions do not have delay slots. Table 53. Unconditional Jump and Call Instructions Instruction...

  • Page 104: Other Control Instructions

    For more information, refer to the “Custom Instructions” section of the Processor Architecture chapter of the Nios II Processor Reference Handbook For continued more information refer to the Nios II Custom Instruction User Guide. Machine-generated C functions and assembly language macros provide access to custom instructions, and hide implementation details from the user.

  • Page 105: No-Operation Instruction

    The Nios II assembler provides a no-operation instruction, 3.9.10. Potential Unimplemented Instructions Some Nios II processor cores do not support all instructions in hardware. In this case, the processor generates an exception after issuing an unimplemented instruction. Only the following instructions can generate an unimplemented instruction exception: •...

  • Page 106: Instantiating The Nios Ii Processor

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 107: Vectors Tab

    NII-PRG | 2018.04.18 Intel FPGA offers the following Nios II cores: • Nios II/f—The Nios II/f fast core is designed for fast performance. As a result, this core presents the most configuration options allowing you to fine tune the processor for performance.

  • Page 108: Exception Vector

    The Exception vector memory list, which includes all memory modules mastered by the Nios II processor, selects the exception vector memory module. In a typical system, select a low-latency memory module for the exception code. Exception vector offset specifies the location of the exception vector relative to the memory module’s base address.

  • Page 109: Caches And Memory Interfaces Tab

    MMU is present. Note: The Nios II MMU is optional and mutually exclusive from the Nios II MPU. Nios II systems can include either an MMU or MPU, but cannot include both an MMU and MPU in the same design.

  • Page 110: Instruction Cache

    Size—Specifies the size of the instruction cache. Valid sizes are from 512 bytes to 64 KBytes, or None. Choosing None disables the instruction cache. The Avalon-MM instruction master port from the Nios II processor will still available. In this case, you must include a tightly-coupled instruction memory. •...

  • Page 111: Flash Accelerator

    Avalon-MM instruction or data masters, software debug is not possible when either the Avalon-MM instruction or data master is omitted. Note: By default this feature is turned on for backwards compatibility with the Nios II Classic core. 4.3.4. Tightly-coupled Memories Number of tightly coupled instruction master port(s) (Include tightly coupled instruction master port(s))—Specifies one to four tightly-coupled instruction master...

  • Page 112: Peripheral Region

    4. Instantiating the Nios II Processor NII-PRG | 2018.04.18 memory ports appear on the connection panel of the Nios II processor on the Platform Designer System Contents tab. You must connect each port to exactly one memory component in the system.

  • Page 113: Arithmetic Implementation

    32-bit multiply instruction selection is set to the 3 16-bit multipliers option. The Nios II only supports up to a 32 x 32 bit multiplication. The 64-bit option is achieved by using the 32-bit multiplier along with the multiply extended...

  • Page 114: Mmu

    When Include MMU on the MMU and MPU Settings tab is on, the MMU settings on the MMU and MPU Settings tab provide the following options for the MMU in the Nios II/f core. Typically, you should not need to change any of these settings from their default values.

  • Page 115: Mpu

    The maximum region size is the size of the Nios II instruction and data addresses automatically determined when the Nios II system is generated in Platform Designer. Maximum region size is based on the address range of slaves connected to the Nios II instruction and data masters.
  • Page 116 Soft processor cores such as the Nios II processor offer unique debug capabilities beyond the features of traditional fixed processors. The soft nature of the Nios II processor allows you to debug a system in development using a full-featured debug core, and later remove the debug features to conserve logic resources.

  • Page 117: Advanced Features Tab

    Nios II Platform Designer Advanced Features Tab 4.7.1. ECC ECC is only available for the Nios II/f core and provides ECC support for Nios II internal RAM blocks, such as instruction cache, MMU TLB, and register file. The SECDED ECC algorithm is based on Hamming codes, which detect 1 or 2 bit errors and corrects 1 bit errors.

  • Page 118: Interrupt Controller Interfaces

    When the EIC interface and shadow register sets are implemented on the Nios II core, you must ensure that your software is built with the Nios II EDS version 9.0 or higher. For details about shadow register sets, refer to “Registers” in the Programming Model chapter of the Nios II Processor Reference Handbook.

  • Page 119: Cpu Id Control Register Value

    4.7.7. Exception Checking The Exception Checking settings provide the following options: Misaligned memory access—Misaligned memory access detection is only available for the Nios II/f core. When Misaligned memory access is on, the processor checks for misaligned memory accesses. Note: When your system contains an MMU or MPU, the processor automatically generates misaligned memory access exceptions.

  • Page 120: Branch Prediction

    However, some complex components generate a separate file, so the .qip system file references the component file. .qip .qip 4.9. Instantiating the Nios II Processor Revision History Document Changes Version 2018.04.18 Implemented editorial enhancements. 2016.10.28 Removed extra exception information option.

  • Page 121: Nios Ii Core Implementation Details

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 122: Nios Ii/F Core

    5.2. Nios II/f Core The Nios II/f fast core is designed for high execution performance. Performance is gained at the expense of core size. Intel FPGA designed the Nios II/f core with the following design goals in mind: •...

  • Page 123: Arithmetic Logic Unit

    Nios II hardware or software designers. 5.2.2. Arithmetic Logic Unit The Nios II/f core provides several arithmetic logic unit (ALU) options to improve the performance of multiply, divide, and shift operations. 5.2.2.1. Multiply and Divide Performance The Nios II/f core provides the following hardware multiplier options: •...

  • Page 124: Memory Access

    Related Information Instruction Performance on page 130 5.2.3. Memory Access The Nios II/f core provides optional instruction and data caches. The cache size for each is user-definable, between 512 bytes and 64 KB. Nios II Processor Reference Guide...
  • Page 125 The core also includes a data cache with a fixed 32-byte line size, making he data master port a pipelined Avalon-MM master port. The instruction and data master ports on the Nios II/f core are optional. A master port can be excluded, as long as the core includes at least one tightly-coupled memory to take the place of the missing master port.
  • Page 126 32 bits and the tag field always includes all the bits of the physical frame number (PFN). The instruction cache is optional. However, excluding instruction cache from the Nios II/f core requires that the core include at least one tightly-coupled instruction memory. 5.2.3.2.2. Data Cache •...

  • Page 127: Tightly-Coupled Memory

    5.2.4. Tightly-Coupled Memory The Nios II/f core provides optional tightly-coupled memory interfaces for both instructions and data. A Nios II/f core can use up to four each of instruction and data tightly-coupled memories. When a tightly-coupled memory interface is enabled, the Nios II core includes an additional memory interface master port.

  • Page 128: Memory Management Unit

    5.2.5. Memory Management Unit The Nios II/f core provides options to improve the performance of the Nios II MMU. For information about the MMU architecture, refer to the Programming Model chapter of the Nios II Processor Reference Handbook.

  • Page 129: Execution Pipeline

    Designers can use this information to minimize unnecessary processor stalling. Most application programmers never need to analyze the performance of individual instructions. The Nios II/f core employs a 6-stage pipeline. Table 67. Implementation Pipeline Stages for Nios II/f Core...

  • Page 130: Instruction Performance

    (if hardware divide is supported), and multicycle custom instructions (if present). 5.2.7.2. Branch Prediction The Nios II/f core performs dynamic and static branch predictions to minimize the cycle penalty associated with taken branches. 5.2.8. Instruction Performance All instructions take one or more cycles to execute. Some instructions have other penalties associated with their execution.

  • Page 131: Exception Handling

    126 • Instruction and Data Caches on page 125 • Arithmetic Logic Unit on page 123 5.2.9. Exception Handling The Nios II/f core supports the following exception types: • Hardware interrupts • Software trap • Illegal instruction •...
  • Page 132 • eic_port_data Signals are rising-edge triggered, and synchronized with the Nios II clock input. The EIC interface presents the following signals to the Nios II processor through the signal: eic_port_data • Requested handler address (RHA)—The 32-bit address of the interrupt handler associated with the requested interrupt.

  • Page 133: Ecc

    5. Nios II Core Implementation Details NII-PRG | 2018.04.18 5.2.10. ECC The Nios II/f core has the option to add ECC support for the following Nios II internal RAM blocks. • Instruction cache — ECC errors (1, 2, or 3 bits) that occur in the instruction cache are recoverable;...

  • Page 134: Jtag Debug Module

    DTCM3_UE 5.2.11. JTAG Debug Module The Nios II/f core supports the JTAG debug module to provide a JTAG interface to software debugging tools. The Nios II/f core supports an optional enhanced interface that allows real-time trace data to be routed out of the processor and stored in an external debug probe.

  • Page 135: Nios Ii/S Core

    NII-PRG | 2018.04.18 5.3. Nios II/s Core The Nios II/s standard core is designed for small core size. On-chip logic and memory resources are conserved at the expense of execution performance. The Nios II/s core uses approximately 20% less logic than the Nios II/f core, but execution performance also drops by roughly 40%.
  • Page 136 None—Does not include multiply hardware. In this case, multiply operations are emulated in software. The Nios II/s core also provides a hardware divide option that includes LE-based divide circuitry in the ALU. Including an ALU option improves the performance of one or more arithmetic instructions.

  • Page 137: Memory Access

    512 bytes and 64 KB. The Nios II/s core can address up to 2 GB of external memory. The Nios II architecture reserves the most-significant bit of data addresses for the bit-31 cache bypass method. In the Nios II/s core, bit 31 is always zero.

  • Page 138: Tightly-Coupled Memory

    The offset field is always five bits (i.e., a 32-byte line). The maximum instruction byte address size is 31 bits. The instruction cache is optional. However, excluding instruction cache from the Nios II/s core requires that the core include at least one tightly-coupled instruction memory. 5.3.4. Tightly-Coupled Memory The Nios II/s core provides optional tightly-coupled memory interfaces for instructions.

  • Page 139: Instruction Performance

    An M-stage multicycle custom instruction is asserting its stall signal. This only occurs if the design includes multicycle custom instructions. 5.3.5.2. Branch Prediction The Nios II/s core performs static branch prediction to minimize the cycle penalty associated with taken branches. 5.3.6. Instruction Performance All instructions take one or more cycles to execute.

  • Page 140: Exception Handling

    Unimplemented instruction 5.3.8. JTAG Debug Module The Nios II/s core supports the JTAG debug module to provide a JTAG interface to software debugging tools. The Nios II/s core supports an optional enhanced interface that allows real-time trace data to be routed out of the processor and stored in an external debug probe.

  • Page 141: Overview

    5.4.3. Memory Access The Nios II/e core does not provide instruction cache or data cache. All memory and peripheral accesses generate an Avalon-MM transfer. The Nios II/e core can address up to 4 GB of external memory, full 32-bit addressing.

  • Page 142: Instruction Performance

    NII-PRG | 2018.04.18 5.4.5. Instruction Performance The Nios II/e core dispatches a single instruction at a time, and the processor waits for an instruction to complete before fetching and dispatching the next instruction. Because each instruction completes before the next instruction is dispatched, branch prediction is not necessary.

  • Page 143: Nios Ii Core Implementation Details Revision History

    5. Nios II Core Implementation Details NII-PRG | 2018.04.18 5.5. Nios II Core Implementation Details Revision History Document Changes Version 2018.04.18 Implemented editorial enhancements. 2017.05.08 Added link to Nios II Performance Benchmarks. 2016.10.28 Maintenance release. 2015.04.02 Initial release Nios II Processor Reference Guide...

  • Page 144: Nios Ii Processor Versions

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 145: Core Revisions

    NII-PRG | 2018.04.18 6.3. Core Revisions Core revisions introduce changes to an existing Nios II core. Core revisions most commonly fix identified bugs, or add support for an architecture revision. Not every Nios II core is revised with every release of the Nios II architecture.

  • Page 146: Application Binary Interface

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 147: Register Usage

    7. Application Binary Interface NII-PRG | 2018.04.18 7.3. Register Usage The ABI adds additional usage conventions to the Nios II register file defined in the Programming Model chapter of the Nios II Processor Reference Handbook. Table 83. Nios II ABI Register Usage...

  • Page 148: Stacks

    Otherwise, it is available as a callee-saved general-purpose register. (44) If the frame pointer is not used, the register is available as a callee-saved temporary register. Refer to “Frame Pointer Elimination” . Nios II Processor Reference Guide...

  • Page 149: Frame Pointer Elimination

    , and . Stack space is not allocated for registers that are not saved. 7.4.3. Further Examples of Stacks There are a number of special cases for stack layout, which are described in this section. Nios II Processor Reference Guide...
  • Page 150 Note: The Nios II C/C++ compiler maintains a frame pointer for any function that calls , even if is spec if ed alloca() -fomit-frame-pointer Figure 14.

  • Page 151: Function Prologues

    These registers, the callee-saved registers, are listed in Nios II ABI Register Usage Table in the Register Usage section. A function prologue is required to save a callee-saved register only if the function uses the register.

  • Page 152: Arguments And Return Values

    An even better way to find out what the prologue has done is to use information stored in the DWARF-2 debugging fields of the executable and linkable format (.elf) file. The instructions found in a Nios II function prologue perform the following tasks: • Adjust the stack pointer (to allocate the frame) •...

  • Page 153: Arguments

    In the example above, if the result type is no larger than 8 bytes, returns its result in If the return type is larger than 8 bytes, the Nios II C/C++ compiler treats this program as if had passed a pointer to .

  • Page 154: Dwarf-2 Definition

    EM_ALTERA_NIOS2 7.8. Relocation In a Nios II object file, each relocatable address reference possesses a relocation type. The relocation type specifies how to calculate the relocated address. The bit mask specifies where the address is found in the instruction.
  • Page 155 R_NIOS2_TLS_GD16 Refer to Thread-Local 0x003FFFC0 Storage section (47) R_NIOS2_TLS_LDM16 Refer to Thread-Local 0x003FFFC0 Storage section continued... (45) For relocation types where no overflow check is performed, the relocated address is truncated to fit the instruction. Nios II Processor Reference Guide...
  • Page 156 G: The offset into the GOT for the GOT slot for symbol S (Linux only) (45) For relocation types where no overflow check is performed, the relocated address is truncated to fit the instruction. (47) Relocation support is provided for Linux systems. Nios II Processor Reference Guide...

  • Page 157: Abi For Linux Systems

    7. Application Binary Interface NII-PRG | 2018.04.18 With the information in the table above, any Nios II instruction can be relocated by manipulating it as an unsigned 32-bit integer, as follows: Xr = (( R << B ) & M | ( X & ~M ));...
  • Page 158 7.9.1.1. Copy Relocation The R_NIOS2_COPY relocation is used to mark variables allocated in the executable that are defined in a shared library. The variable’s initial value is copied from the shared library to the relocated location. Nios II Processor Reference Guide...
  • Page 159 165 7.9.1.3. Thread-Local Storage The Nios II processor uses the Variant I model for thread-local storage. The end of the thread control block (TCB) is located 0x7000 bytes before the thread pointer. The TCB is eight bytes long. The first word is the dynamic thread pointer (DTV) pointer and the second word is reserved.

  • Page 160: Linux Function Calls

    64 KB. This option is separate from -G 0, because -G 0 creates ABI incompatibility. A file compiled with -G 0 puts global variables into but files compiled with - .data G 8 expect such variables to be in .sdata Nios II Processor Reference Guide...

  • Page 161: Linux Operating System Call Interface

    For information about userspace debugging, refer to "Userspace Breakpoints”. The page size is 4 KB. Virtual addresses in user mode are all below 2 GB due to the MMU design. The NULL page is not mapped. Related Information Userspace Breakpoints on page 167 Nios II Processor Reference Guide...

  • Page 162: Linux Process Initialization

    %lo(_gp_got - 1b) # R_NIOS2_PCREL_LO _gp_got - 4 add r22, r22, r1 # GOT pointer in r22 Data may be accessed by loading its location from the GOT. A single word GOT entry is generated for each referenced symbol. Nios II Processor Reference Guide...
  • Page 163 Example 20. Small GOT Model entry in PLT GOT r3, %call(fun)(r22) # R_NIOS2_CALL16 fun callr PLTGOT[n] R_NIOS_JUMP_SLOT fun Example 21. Large GOT Model entry in PLT GOT movhi r3, %call_hiadj(x) # R_NIOS2_CALL_HA addi r3, r3, %call_lo(x) # R_NIOS2_CALL_LO r3, r3, r22 r3, 0(r3) Nios II Processor Reference Guide...

  • Page 164: Linux Program Loading And Dynamic Linking

    GOT. The linker-defined symbol points to the base _gp_got address used for GOT-relative relocations. The value of might vary between _gp_got object files if the linker creates multiple GOT sections. Nios II Processor Reference Guide...
  • Page 165 In front of the initial PLT entry, a series of branches start of the initial entry (the instruction). There is one branch for each PLT entry, labelled through nextpc res_0 . The last several branches may be replaced by instructions to improve res_N Nios II Processor Reference Guide...
  • Page 166 Example 29. Initial PLT Entry Out of Range .PLTn: orhi r15, r0, %hiadj(index * 4) addi r15, r15, %lo(index * 4) nextpc orhi r13, r0, %hiadj(_GLOBAL_OFFSET_TABLE_) r13, r13, r14 r14, %lo(_GLOBAL_OFFSET_TABLE_+4)(r13) r13, %lo(_GLOBAL_OFFSET_TABLE_+8)(r13) 7.9.6.4. Linux Program Interpreter The program interpreter is /lib/ld.so.1. Nios II Processor Reference Guide...

  • Page 167: Linux Conventions

    7.9.7.3. Atomic Operations The Nios II architecture does not have atomic operations (such as load linked and store conditional). Atomic operations are emulated using a kernel system call via the instruction. The toolchain provides intrinsic functions which perform the system trap call.

  • Page 168: Application Binary Interface Revision History

    NII-PRG | 2018.04.18 The object macro is predefined to 1 when you compile a program __nios2_arch__ for Nios II R1 ISA and is predefined to 2 when you compile for Nios II R2 ISA. 7.11. Application Binary Interface Revision History Document Changes Version 2018.04.18...

  • Page 169: Instruction Set Reference

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 170: J-Type

    IMM26 8.2. Instruction Opcodes The OP field in the Nios II instruction word specifies the major class of an opcode as listed in the two tables below. Most values of OP are encodings for I-type instructions. One encoding, OP = 0x00, is the J-type instruction .
  • Page 171 0x29 initi 0x39 0x0A 0x1A srli 0x2A 0x3A srai 0x0B 0x1B 0x2B 0x3B 0x0C flushi 0x1C nextpc 0x2C 0x3C 0x0D 0x1D callr 0x2D trap 0x3D 0x0E 0x1E 0x2E wrctl 0x3E 0x0F 0x1F mulxss 0x2F 0x3F Nios II Processor Reference Guide...

  • Page 172: Assembler Pseudo-Instructions

    146 8.4. Assembler Macros The Nios II assembler provides macros to extract halfwords from labels and from 32- bit immediate values. These macros return 16-bit signed values or 16-bit unsigned values depending on where they are used. When used with an instruction that requires...

  • Page 173: Instruction Set Reference

    Replace the immed32 address with an offset from immed32 –_gp %gprel(immed32) the global pointer Refer to the Application Binary Interface chapter of the Nios II Processor Reference Handbook for more information about global pointers. Related Information Application Binary Interface on page 146 8.5.

  • Page 174: Add

    Double TLB miss (instruction) • TLB permission violation (execute) • MPU region violation (instruction) For information about these and all Nios II exceptions, refer to the Programming Model chapter of the Nios II Processor Reference Handbook. Related Information Programming Model on page 36 8.5.1.

  • Page 175: Addi

    IMM16 cmpltu rD, rB, rA addi rB, rA, IMM16 bltu rB, rA, label # The original add operation # rD is written with the carry bit # The original add operation continued... Nios II Processor Reference Guide...

  • Page 176: And

    Calculates the bitwise logical AND of rA and rB and stores the result in rC. Exceptions None Instruction Type Instruction Fields = Register index of operand rA = Register index of operand rB = Register index of operand rC Nios II Processor Reference Guide...

  • Page 177: Andhi

    Calculates the bitwise logical AND of rA and (0x0000 : IMM16) and stores the result in rB. Exceptions None Instruction Type Instruction Fields = Register index of operand rA = Register index of operand rB = 16-bit unsigned immediate value IMM16 Nios II Processor Reference Guide...

  • Page 178: Beq

    If (signed) rA >= (signed) rB, then transfers program control to the instruction at label. In the instruction encoding, the offset given by IMM16 is treated as a signed number of bytes relative to the instruction immediately continued... Nios II Processor Reference Guide...

  • Page 179: Bgeu

    = Register index of operand rA = Register index of operand rB = 16-bit signed immediate value IMM16 Bit Fields IMM16 IMM16 0x2e 8.5.9. bgt Instruction branch if greater than signed Operation if ((signed) rA > (signed) rB) continued... Nios II Processor Reference Guide...

  • Page 180: Bgtu

    8.5.12. bleu Instruction branch if less than or equal to unsigned Operation if ((unsigned) rA <= (unsigned) rB) then PC label else PC PC + 4 Assembler Syntax bleu rA, rB, label continued... Nios II Processor Reference Guide...

  • Page 181: Blt

    IMM16 is treated as a signed number of bytes relative to the instruction immediately following . The two least-significant bits of IMM16 are bltu always zero, because instruction addresses must be word- aligned. continued... Nios II Processor Reference Guide...

  • Page 182: Bne

    = Register index of operand rB = 16-bit signed immediate value IMM16 Bit Fields IMM16 IMM16 0x1e 8.5.16. br Instruction unconditional branch Operation PC + 4 + σ(IMM16) Assembler Syntax br label Example br top_of_loop continued... Nios II Processor Reference Guide...

  • Page 183: Break

    Nios_II Processor parameter editor in Platform Designer. Some debuggers support instructions break break 0 in source code. These debuggers treat the instruction break as a normal breakpoint. Exceptions Break Instruction Type Instruction Fields = Type of breakpoint IMM5 Nios II Processor Reference Guide...

  • Page 184: Bret

    IMM26 x 4). Usage can transfer execution anywhere within the 256-MB call range determined by PC . The Nios II GNU linker does 31..28 not automatically handle cases in which the address is out of this range. continued... Nios II Processor Reference Guide...

  • Page 185: Callr

    If rA == rB, then stores 1 to rC; otherwise, stores 0 to rC. Usage performs the == operation of the C programming cmpeq language. Also, can be used to implement the C cmpeq logical negation operator “!”. continued... Nios II Processor Reference Guide...

  • Page 186: Cmpeqi

    = Register index of operand rB = 16-bit signed immediate value IMM16 Bit Fields IMM16 IMM16 0x20 8.5.23. cmpge Instruction compare greater than or equal signed Operation if ((signed) rA >= (signed) rB) then rC continued... Nios II Processor Reference Guide...

  • Page 187: Cmpgei

    >= operation of the C cmpgei programming language. Exceptions None Instruction Type Instruction Fields = Register index of operand rA = Register index of operand rB = 16-bit signed immediate value IMM16 Bit Fields IMM16 IMM16 0x08 Nios II Processor Reference Guide...

  • Page 188: Cmpgeu

    >= operation of the C cmpgeui programming language. Exceptions None Instruction Type Instruction Fields = Register index of operand rA = Register index of operand rB = 16-bit unsigned immediate value IMM16 Nios II Processor Reference Guide...

  • Page 189: Cmpgt

    IMM16 immediate value of IMMED + 1. 8.5.29. cmpgtu Instruction compare greater than unsigned Operation if ((unsigned) rA > (unsigned) rB) then rC else rC Assembler Syntax cmpgtu rC, rA, rB continued... Nios II Processor Reference Guide...

  • Page 190: Cmpgtui

    8.5.32. cmplei Instruction compare less than or equal signed immediate Operation if ((signed) rA < (signed) IMMED) then rB else rB Assembler Syntax cmplei rB, rA, IMMED continued... Nios II Processor Reference Guide...

  • Page 191: Cmpleu

    IMM16 immediate value of IMMED + 1. 8.5.35. cmplt Instruction compare less than signed Operation if ((signed) rA < (signed) rB) then rC else rC continued... Nios II Processor Reference Guide...

  • Page 192: Cmplti

    < operation of the C cmplti programming language. Exceptions None Instruction Type Instruction Fields = Register index of operand rA = Register index of operand rB = 16-bit signed immediate value IMM16 Bit Fields IMM16 IMM16 0x10 Nios II Processor Reference Guide...

  • Page 193: Cmpltu

    < operation of the C cmpltui programming language. Exceptions None Instruction Type Instruction Fields = Register index of operand rA = Register index of operand rB = 16-bit unsigned immediate value IMM16 Nios II Processor Reference Guide...

  • Page 194: Cmpne

    If rA != σ(IMM16), then stores 1 to rB; otherwise stores 0 to rB. cmpnei Usage performs the != operation of the C programming cmpnei language. continued... Nios II Processor Reference Guide...

  • Page 195: Custom

    Description opcode provides access to up to 256 custom custom instructions allowed by the Nios II architecture. The function implemented by a custom instruction is user-defined and is specified with the Nios_II Processor parameter editor in Platform Designer. The 8-bit immediate N field specifies which custom instruction to use.

  • Page 196: Div

    After dividing –2147483648 by –1, the value of rC is undefined (the number +2147483648 is not representable in 32 bits). There is no overflow exception. Nios II processors that do not implement the instruction cause an unimplemented instruction exception. Usage...

  • Page 197: Divu

    After attempted division by zero, the value of rC is undefined. There is no divide-by-zero exception. Nios II processors that do not implement the divu instruction cause an unimplemented instruction exception. Usage...

  • Page 198: Flushd

    • Clear the valid bit for the line. If the Nios II processor core does not have a data cache, instruction performs no operation. flushd Usage...

  • Page 199: Flushda

    • Clear the valid bit for the line. If the Nios II processor core does not have a data cache, instruction performs no operation. flushda continued... Nios II Processor Reference Guide...

  • Page 200: Flushi

    “initd initialize data cache line”, and “initda initialize data cache address” for other cache-clearing options. For more information on the Nios II data cache, refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook.

  • Page 201: Flushp

    Assembler Syntax initd IMM16(rA) Example initd 0(r6) Description If the Nios II processor implements a direct mapped data cache, clears the data cache line without checking initd for (or writing) a dirty data cache line that is mapped to the specified address back to memory.
  • Page 202 • Clear the valid bit for the line. If the Nios II processor core does not have a data cache, instruction performs no operation. initd Usage after processor reset and before accessing data initd memory to initialize the processor’s data cache.

  • Page 203: Initda

    • Clear the valid bit for the line. If the Nios II processor core does not have a data cache, instruction performs no operation. initda Usage to skip writing dirty lines back to memory and...

  • Page 204: Initi

    , and initi invalidates that line. If the Nios II processor core does not have an instruction cache, the instruction performs no operation. initi Usage This instruction is used to initialize the processor’s instruction cache.

  • Page 205: Jmp

    256-MB range determined by . The Nios II GNU linker does not automatically 31..28 handle cases in which the address is out of this range. Exceptions None...

  • Page 206: Ldb / Ldbio

    16-bit immediate value. Loads register rB with the desired memory byte, sign extending the 8-bit value to 32 bits. In Nios II processor cores with a data cache, this instruction may retrieve the desired data from the cache instead of from memory.

  • Page 207: Ldbu / Ldbuio

    In processors without a data cache, acts like ldbuio ldbu For more information on data cache, refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook. Exceptions Supervisor-only data address Misaligned data address TLB permission violation (read)

  • Page 208: Ldh / Ldhio

    Avalon-MM data transfer. In processors without a data cache, acts like ldhio For more information on data cache, refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook. Exceptions Supervisor-only data address Misaligned data address...

  • Page 209: Ldhu / Ldhuio

    In processors without a data cache, acts like ldhuio ldhu For more information on data cache, refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook. Exceptions Supervisor-only data address Misaligned data address TLB permission violation (read)

  • Page 210: Ldw / Ldwio

    Avalon-MM data transfer. In processors without a data cache, acts like ldwio For more information on data cache, refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook. Exceptions Supervisor-only data address Misaligned data address...

  • Page 211: Mov

    16 bits with an instruction. The % macro can be lo() used to extract the lower 16 bits of a constant or label as shown in the following code: movhi rB, %hi(value) ori rB, rB, %lo(value) continued... Nios II Processor Reference Guide...

  • Page 212: Movi

    The maximum allowed value of IMMED is 65535. The minimum allowed value is 0. To load a 32-bit constant into a register, refer to the instruction. movhi Pseudo-instruction is implemented as movui ori rB, r0, IMMED Nios II Processor Reference Guide...

  • Page 213: Mul

    Multiplies rA times rB and stores the 32 low-order bits of the product to rC. The result is the same whether the operands are treated as signed or unsigned integers. Nios II processors that do not implement the instruction cause an unimplemented instruction exception. Usage...

  • Page 214: Muli

    Stores the 32 low-order bits of the product to rB. The result is independent of whether rA is treated as a signed or unsigned number. Nios II processors that do not implement the muli instruction cause an unimplemented instruction exception.

  • Page 215: Mulxsu

    32 mulxsu high-order bits of the product to rC. Nios II processors that do not implement the mulxsu instruction cause an unimplemented instruction exception. Usage can be used as part of the calculation of a 128-bit mulxsu product of two 64-bit signed integers.

  • Page 216: Nextpc

    Treating rA and rB as unsigned integers, multiplies mulxuu rA times rB and stores the 32 high-order bits of the product to rC. Nios II processors that do not implement the mulxuu instruction cause an unimplemented instruction exception. Usage to compute the 64-bit product of two mulxuu 32-bit unsigned integers.

  • Page 217: Nop

    Operation rA | rB Assembler Syntax or rC, rA, rB Example or r6, r7, r8 Description Calculates the bitwise logical OR of rA and rB and stores the result in rC. continued... Nios II Processor Reference Guide...

  • Page 218: Orhi

    | (0x0000 : IMM16) Assembler Syntax ori rB, rA, IMM16 Example ori r6, r7, 100 Description Calculates the bitwise logical OR of rA and (0x0000 : IMM16) and stores the result in rB. continued... Nios II Processor Reference Guide...

  • Page 219: Rdctl

    Places the result in rB in the current register set. Usage The previous register set is specified by status.PRS. By default, status.PRS indicates the register set in use before an exception, such as an external interrupt, caused a register set change. continued... Nios II Processor Reference Guide...

  • Page 220: Ret

    To read from an arbitrary register set, software can insert the desired register set number in prior to status.PRS executing rdprs If shadow register sets are not implemented on the Nios II core, is an illegal instruction. rdprs Exceptions Supervisor-only instruction...

  • Page 221: Roli

    = Register index of operand rC = 5-bit unsigned immediate value IMM5 Bit Fields 0x02 0x02 IMM5 0x3a 8.5.80. ror Instruction rotate right Operation rA rotated right rB bit positions 4..0 Assembler Syntax ror rC, rA, rB continued... Nios II Processor Reference Guide...

  • Page 222: Sll

    = Register index of operand rB = Register index of operand rC Bit Fields 0x13 0x13 0x3a 8.5.82. slli Instruction shift left logical immediate Operation rA << IMM5 Assembler Syntax slli rC, rA, IMM5 continued... Nios II Processor Reference Guide...

  • Page 223: Sra

    = Register index of operand rA = Register index of operand rB = Register index of operand rC Bit Fields 0x3b 0x3b 0x3a 8.5.84. srai Instruction shift right arithmetic immediate Operation (signed) rA >> ((unsigned) IMM5) continued... Nios II Processor Reference Guide...

  • Page 224: Srl

    >> operation of the C programming language. Exceptions None Instruction Type Instruction Fields = Register index of operand rA = Register index of operand rB = Register index of operand rC Bit Fields 0x1b 0x1b 0x3a Nios II Processor Reference Guide...

  • Page 225: Srli

    Avalon-MM data transfer. In processors without a data cache, acts like stbio Exceptions Supervisor-only data address Misaligned data address TLB permission violation (write) Fast TLB miss (data) Double TLB miss (data) continued... Nios II Processor Reference Guide...

  • Page 226: Sth / Sthio

    Exceptions Supervisor-only data address Misaligned data address TLB permission violation (write) Fast TLB miss (data) Double TLB miss (data) MPU region violation (data) Instruction Type Instruction Fields = Register index of operand rA continued... Nios II Processor Reference Guide...

  • Page 227: Stw / Stwio

    TLB permission violation (write) Fast TLB miss (data) Double TLB miss (data) MPU region violation (data) Instruction Type Instruction Fields = Register index of operand rA = Register index of operand rB = 16-bit signed immediate value IMM16 Nios II Processor Reference Guide...

  • Page 228: Sub

    # The original sub operation continued... Nios II Processor Reference Guide...

  • Page 229: Subi

    Description Forces all pending memory accesses to complete before allowing execution of subsequent instructions. In processor cores that support in-order memory accesses only, this instruction performs no operation. Exceptions None Instruction Type Instruction Fields None Nios II Processor Reference Guide...

  • Page 230: Trap

    Instruction Type Instruction Fields = Type of breakpoint IMM5 Bit Fields 0x1d 0x2d 0x2d IMM5 0x3a 8.5.94. wrctl Instruction write to control register Operation ctlN Assembler Syntax wrctl ctlN, rA Example wrctl ctl6, r3 continued... Nios II Processor Reference Guide...

  • Page 231: Wrprs

    System software must use to initialize to 0 in wrprs each shadow register set before using that register set. If shadow register sets are not implemented on the Nios II core, is an illegal instruction. wrprs Exceptions Supervisor-only instruction...

  • Page 232: Xor

    (IMM16 : 0x0000) and stores the result in rB. Exceptions None Instruction Type Instruction Fields = Register index of operand rA = Register index of operand rB = 16-bit unsigned immediate value IMM16 Bit Fields IMM16 IMM16 0x3c Nios II Processor Reference Guide...

  • Page 233: Xori

    = Register index of operand rB = 16-bit unsigned immediate value IMM16 Bit Fields IMM16 IMM16 0x1c 8.6. Instruction Set Reference Revision History Document Changes Version 2018.04.18 Implemented editorial enhancements. 2016.10.28 Maintenance release. 2015.04.02 Initial release Nios II Processor Reference Guide...

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