Ecc - Intel NIOS II Owner Reference Manual

5. Nios II Core Implementation Details
NII-PRG | 2018.04.18

5.2.10. ECC

The Nios II/f core has the option to add ECC support for the following Nios II internal
RAM blocks.
• Instruction cache
— ECC errors (1, 2, or 3 bits) that occur in the instruction cache are recoverable;
the Nios II processor flushes the cache line and reads from external memory
instead of correcting the ECC error.
• Register file
— 1 bit ECC errors are recoverable
— 2 bit ECC errors are not recoverable and generate ECC exceptions
• MMU TLB
— 1 bit ECC errors triggered by hardware reads are recoverable
— 2 bit ECC errors triggered by hardware reads are not recoverable and generate
ECC exception.
— 1 or 2 bit ECC errors triggered by software reads to the
not trigger an exception, instead,
this field and invalidate/overwrite the TLB entry.
• Data Cache
— tag RAM—The
RAM.
— data RAM—The
RAM
• Tightly-Coupled Memories (TCMs)—Nios II includes the ECC encoder/decoder logic
for each TCM and the TCM master port data width is increased to allow the Nios II
to read and write the ECC parity bits.The TCM must be a RAM and must store the
ECC parity bits along with the data bits.
— Instruction Tightly-Coupled Memories (ITCM)—Nios II supports up to 4 ITCMs
— Data Tightly-Coupled Memories (DTCM)—Nios II supports up to 4 DTCMs
The ECC interface is an Avalon-ST source with the output signal
This interface allows external logic to monitor ECC errors in the Nios II processor.
Table 70. ECC Error Signals
Bit Field
0
EEH
1
RF_RE
2
RF_UE
3
ICTAG_RE
4
ICDAT_RE
field is used to inject ECC errors into the tag
ECCINJ.DCTAG
field is used to inject ECC errors into the data
ECCINJ.DCDAT
Description
ECC error exception while in exception handler mode (i.e.,
= 1).
Recoverable (1 bit) ECC error in register file RAM
Unrecoverable (2 bit) ECC error in register file RAM
Recoverable (1, 2, or 3 bit) ECC error in instruction cache tag RAM
Recoverable (1, 2, or 3 bit) ECC error in instruction cache data RAM.
TLBMISC
is set to 1. Software must read
TLBMISC.EE
ecc_event_bus
STATUS.EH
Nios II Processor Reference Guide
register do
.
Effect on Available
Software
Likely fatal Always
None Always
Likely fatal Always
None Instruction cache
present
None Instruction cache
present
continued...
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