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3. Programming Model
NII-PRG | 2018.04.18
Related Information
Nios II Core Implementation Details
3.8.1. Cache Memory
The Nios II architecture and instruction set accommodate the presence of data cache
and instruction cache memories. Cache management is implemented in software by
using cache management instructions. Instructions are provided to initialize the cache,
flush the caches whenever necessary, and to bypass the data cache to properly access
memory-mapped peripherals.
The Nios II architecture provides the following mechanisms to bypass the cache:
•
When no MMU is present, bit 31 of the address is reserved for the optinal bit-31
cache bypass. With bit-31 cache bypass, the address space of processor cores is
2 GB, and the high bit of the address controls the caching of data memory
accesses.
•
When the MMU is present, cacheability is controlled by the MMU, and bit 31
functions as a normal address bit. For details, refer to the Address Space and
Memory Partitions section , and the TLB Organization section of this chapter.
•
Cache bypass instructions, such as
Refer to the Nios II Core Implementation Details chapter of the Nios II Processor
Reference Handbook for details of which processor cores implement bit-31 cache
bypass.
Refer to Instruction Set Reference chapter of the Nios II Processor Reference
Handbook for details of the cache bypass instructions.
Code written for a processor core with cache memory behaves correctly on a
processor core without cache memory. The reverse is not true. If it is necessary for a
program to work properly on multiple Nios II processor core implementations, the
program must behave as if the instruction and data caches exist. In systems without
cache memory, the cache management instructions perform no operation, and their
effects are benign.
For a complete discussion of cache management, refer to theCache and Tightly
Coupled Memory chapter of the Nios II Software Developer's Handbook.
Some consideration is necessary to ensure cache coherency after processor reset.
Refer to "Reset Exceptions" section of this chapter for more information.
For information about the cache architecture and the memory hierarchy refer to the
Processor Architecture chapter of the Nios II Processor Reference Handbook.
Related Information
•
Cache and Tightly Coupled Memory
•
Reset Exceptions
•
TLB Organization
•
Address Space and Memory Partitions
•
Instruction Set Reference
•
Processor Architecture
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Nios II Processor Reference Guide
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