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the value written into
tlbmisc.PID
software to quickly modify TLB entries.
Issuing a
register. The
read operation (that is, when
Table 23.
tlbacc Control Register Field Descriptions
Field
is ignored by hardware and available to hold operating system
IG
IG
specific information. Read as zero but can be written as nonzero.
is the data cacheable flag. When
C
C
uncacheable. When
is the readable flag. When
R
R
access memory. When
memory.
is the writable flag. When
W
W
access memory. When
memory.
is the executable flag. When
X
X
execute. When
is the global flag. When
G
G
lookup. When
page number is used in the TLB lookup.
is the physical frame number field. All unused upper bits must be
PFN
PFN
zero.
The
tlbacc
system page table. The
read back as zero on
to hold operating system specific information without having to clear these bits to zero
on a TLB write operation.
3.4.2.10. The tlbmisc Register
The
tlbmisc
in systems with an MMU.
Table 24.
tlbmisc Control Register Fields
31
30
29
Reserved
15
14
13
Nios II Processor Reference Guide
54
along with the values of
tlbacc
. A TLB write operation also increments
instruction to the
rdctl
register is written by hardware when software triggers a TLB
tlbacc
wrctl
Description
= 0, data accesses are
C
= 1, data accesses are cacheable.
C
= 0, load instructions are not allowed to
R
= 1, load instructions are allowed to access
R
= 0, store instructions are not allowed to
W
= 1, store instructions are allowed to access
W
= 0, instructions are not allowed to
X
= 1, instructions are allowed to execute.
X
= 0,
G
tlbmisc.PID
= 1,
is ignored and only the virtual
G
tlbmisc.PID
register format is the recommended format for entries in the operating
bits are ignored by the hardware on
IG
from
rdctl
register contains the remaining TLB-related fields and is only available
28
27
26
25
12
11
10
9
PID
pteaddr.VPN
tlbmisc.WAY
register returns the value of the
tlbacc
sets
to one).
tlbmisc.RD
is included in the TLB
. The operating system can use the
tlbacc
Bit Fields
24
23
22
21
EE
WAY
8
7
6
5
3. Programming Model
NII-PRG | 2018.04.18
and
, allowing
tlbacc
Access
Reset
Availabl
Read/Write
0
Only
with
MMU
Read/Write
0
Only
with
MMU
Read/Write
0
Only
with
MMU
Read/Write
0
Only
with
MMU
Read/Write
0
Only
with
MMU
Read/Write
0
Only
with
MMU
Read/Write
0
Only
with
MMU
to
wrctl
tlbacc
IG
20
19
18
17
RD
WE
PID
4
3
2
1
DBL
BAD
PERM
e
and
bits
16
0
D
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