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Bit
is the interrupt handler mode bit. The processor sets
IH
IH
when it takes an external interrupt.
(8)
is the exception handler mode bit. The processor sets
EH
EH
when an exception occurs (including breaks). Software clears
zero when ready to handle exceptions again.
to determine whether a TLB miss exception is a fast TLB miss or a
double TLB miss. In systems without an MMU,
(8)
is the user mode bit. When
U
U
mode. When
systems without an MMU,
is the processor interrupt-enable bit. When
PIE
PIE
maskable external interrupts and noninterrupt exceptions are ignored.
When
PIE
taken, depending on the status of the interrupt controller.
Noninterrupt exceptions are unaffected by
Related Information
External Interrupt Controller Interface
3.4.2.2. The estatus Register
The
estatus
exception processing.
Table 16.
estatus Control Register Fields
31
30
29
28
15
14
13
12
CRS
All fields in the
When the Nios II processor takes an interrupt, if
is in nonexception mode), the processor copies the contents of the
.
estatus
Note:
If shadow register sets are implemented, and the interrupt requests a shadow register
set, the Nios II processor copies status to
For details about the
(8)
The state where both
(9)
When this field is unimplemented, the field value always reads as 0, and the processor behaves
accordingly.
Nios II Processor Reference Guide
50
Description
= 1, the processor operates in user
U
= 0, the processor operates in supervisor mode. In
U
is always zero.
U
= 1, internal and maskable external interrupts can be
register holds a saved copy of the
Bit Fields
27
26
25
24
Reserved
11
10
9
8
register have read/write access. All fields reset to 0.
estatus
register, refer to The sstatus Register section.
sstatus
and
are one is illegal and causes undefined results.
EH
U
Read/Write
to one
IH
Read/Write
to one
EH
to
EH
is used by the MMU
EH
is always zero.
EH
Read/Write
= 0, internal and
Read/Write
PIE
.
PIE
on page 80
register during nonbreak
status
23
22
21
20
RSIE
NMI
7
6
5
4
IL
status.eh
, not to
sstatus
estatus
3. Programming Model
NII-PRG | 2018.04.18
Access
Reset
0
EIC interface only
0
MMU or ECC only
0
MMU or MPU only
0
Always
19
18
17
16
PRS
3
2
1
0
IH
EH
U
PIE
is zero (that is, the MMU
register to
status
.
Available
(9)
(9)
(9)
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