Intel NIOS II Owner Reference Manual page 92

Processor Status Register
or Field
tlbmisc.DBL (34)
tlbmisc.PERM (34)
tlbmisc.BAD (34)
status.PIE
status.EH (34)
status.IH (40)
status.NMI (40)
status.IL (40)
status.RSIE (35)(40)
status.CRS (35)
status.U (34)
(19) If the Nios II processor does not have an EIC interface, external interrupts do not occur.
(28) Set to 1 on a double TLB miss, set to 0 otherwise
(29) Set to 1 on a TLB permission violation, set to 0 otherwise
(30) Set to 1 on a bad virtual address exception, set to 0 otherwise
(31) Disables exceptions and nonmaskable interrupts
(32) If the MMU is implemented, indicates that the processor is handling an exception.
(33) Puts the processor in supervisor mode.
(34)
If the Nios II processor does not have an MMU, this field is not implemented. Its value is always
0, and the processor behaves accordingly.
(35)
If the Nios II processor does not have shadow register sets, this field is not implemented. Its
value is always 0, and the processor behaves accordingly.
(36)
If the Nios II processor does not have an MMU, TLB-related exceptions do not occur.
(37)
The pre-exception value
(38)
Saves the processor's pre-exception status
(39)
If the MMU is implemented, indicates that the processor is handling an exception.
(40)
If the Nios II processor does not have an EIC interface, this field is not implemented.
Nios II Processor Reference Guide
92
External Interrupt Asserted (19)
status.EH==1 (34)
status.EH==0
RRS==0 (
RRS!=0 RRS==0
35)
No change
No change
No change
No change
No change
1
RNMI
RIL
0
RRS
0 (33)
System Status Before Taking Exception
Internal Interrupt Asserted or Noninterrupt Exception
status.EH==1
RRS!=0
0 (31)
1 (32)
No change
No change
No change
No change
No change
3. Programming Model
NII-PRG | 2018.04.18
status.EH==0
TLB No TLB Miss
Miss (36)
TLB
Permission
Violation (36)
(28)
(29)
(30)
No TLB
Permission
Violation