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3. Programming Model
NII-PRG | 2018.04.18
3.4.2.10.6. The BAD Flag
During a general exception, the processor sets
condition exists, and clears
flag to one:
BAD
•
Supervisor-only instruction address
•
Supervisor-only data address
•
Misaligned data address
•
Misaligned destination address
Refer to Nios II Exceptions (In Decreasing Priority Order) table in the "Exception
Overview" section for more information on these exceptions.
Related Information
Exception Overview
3.4.2.10.7. The PERM Flag
During a general exception, the processor sets
violation exception, and clears
3.4.2.10.8. The D Flag
The
flag indicates whether the exception is an instruction access exception or a data
D
access exception. During a general exception, the processor sets
exception is related to a data access, and clears
exceptions.
The following exceptions set the
•
Fast TLB miss (data)
•
Double TLB miss (data)
•
TLB permission violation (read or write)
•
Misaligned data address
•
Supervisor-only data address
3.4.2.11. The badaddr Register
Nios II/f processor provides information useful to system software for exception
processing in the exception and badaddr registers when an exception occurs.
Note:
The exception register is not available for Nios II/e core, therefore you cannot add a
MMU or MPU to the processor configuration. For more information, refer to the Nios II
Core Implementation Details chapter of this document.
When an exception occurs in Nios II/f processor, the
byte instruction or data address associated with certain exceptions at the time the
exception occurred. The Nios II Exceptions Table lists which exceptions write the
badaddr
to zero otherwise. The following exceptions set the
BAD
on page 75
PERM
D
register along with the value written.
to one when a bad virtual address
BAD
to one for a TLB permission
PERM
to zero otherwise.
to zero for all other nonbreak
D
flag to one:
badaddr
to one when the
D
register contains the
Nios II Processor Reference Guide
57
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