Intel NIOS II Owner Reference Manual page 84

• Supervisor-only data address
• Misaligned data address
• Misaligned destination address
• Division error
• Fast TLB miss
• Double TLB miss
• TLB permission violation
• MPU region violation
Note: All noninterrupt exception handlers must run in the normal register set.
Related Information
Exception Processing Flow
3.7.7.1. Trap Instruction
When a program issues the
exception. A program typically issues a software trap when the program requires
servicing by the operating system. The general exception handler for the operating
system determines the reason for the trap and responds appropriately.
3.7.7.2. Break Instruction
The break instruction is treated as a break exception. For more information, refer to
the "Break Exceptions" section of this chapter.
Related Information
Break Exceptions
3.7.7.3. Unimplemented Instruction
When the processor issues a valid instruction that is not implemented in hardware, an
unimplemented instruction exception is generated. The general exception handler
determines which instruction generated the exception. If the instruction is not
implemented in hardware, control is passed to an exception routine that might choose
to emulate the instruction in software.
For more information, refer to the "Potential Unimplemented Instructions" section of
this chapter.
Related Information
Potential Unimplemented Instructions
3.7.7.4. Illegal Instruction
Illegal instructions are instructions with an undefined opcode or opcode-extension
field. The Nios II processor can check for illegal instructions and generate an exception
when an illegal instruction is encountered. Illegal instruction checking is always on
regardless of MMU or MPU settings.
Nios II Processor Reference Guide
84
on page 88
instruction, the processor generates a software trap
trap
on page 78
on page 105
3. Programming Model
NII-PRG | 2018.04.18