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8. Instruction Set Reference
NII-PRG | 2018.04.18
Exceptions
Instruction Type
Instruction Fields
31
30
29
A
15
14
13
Related Information
•
Cache and Tightly-Coupled Memory
•
flushda
•
initda
•
initd
8.5.46. flushda
Instruction
Operation
Assembler Syntax
Example
Description
28
27
26
25
12
11
10
9
IMM16
on page 199
on page 203
on page 201
None
I
= Register index of operand rA
A
= 16-bit signed immediate value
IMM16
Bit Fields
24
23
22
21
0
8
7
6
5
flush data cache address
Flushes the data cache line currently caching address
rA + σ(IMM16)
flushda IMM16(rA)
flushda -100(r6)
If the Nios II processor implements a direct mapped data
cache,
writes the data cache line that is mapped
flushda
to the specified address back to memory if the line is dirty,
and then clears the data cache line. Unlike
writes the dirty data back to memory only when
flushda
the addressed data is currently in the cache. This process
comprises the following steps:
•
Compute the effective address specified by the sum of rA
and the signed 16-bit immediate value.
•
Identify the data cache line associated with the
computed effective address. Each data cache effective
address comprises a
identifying the line,
and the
field.
line
•
Compare the cache line tag with the effective address to
determine if the addressed data is currently cached. If
the
fields do not match, the effective address is not
tag
currently cached, so the instruction does nothing.
•
If the data cache line is dirty and the
write the dirty cache line back to memory. A cache line is
dirty when one or more words of the cache line have
been modified by the processor, but are not yet written
to memory.
•
Clear the valid bit for the line.
If the Nios II processor core does not have a data cache,
the
instruction performs no operation.
flushda
20
19
18
17
IMM16
4
3
2
1
0x3b
,
flushd
field and a
field. When
tag
line
uses both the
field
flushda
tag
fields match,
tag
continued...
Nios II Processor Reference Guide
16
0
199
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