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3.7.7.13. TLB Permission Violation
TLB permission violation exceptions are implemented only in Nios II processors that
include the MMU. When a TLB entry is found matching the VPN (optionally extended
by a process identifier), but the permissions do not allow the access to complete, a
TLB permission violation exception is generated.
There are three kinds of TLB permission violation exceptions:
•
TLB permission violation (execute)—Any instruction fetch can cause this exception.
•
TLB permission violation (read)—Any load instruction can cause this exception.
•
TLB permission violation (write)—Any store instruction can cause this exception.
The general exception handler can inspect the
which permissions were violated.
Note:
The data cache management instructions (
ignore the TLB permissions and do not generate TLB permission violation exceptions.
3.7.7.14. MPU Region Violation
MPU region violation exceptions are implemented only in Nios II processors that
include the MPU. An MPU region violation exception is generated under any of the
following conditions:
•
An instruction fetch or data address matched a region but the permissions for that
region did not allow the action to complete.
•
An instruction fetch or data address did not match any region.
The general exception handler reads the MPU region attributes to determine if the
address did not match any region or which permissions were violated.
There are two kinds of MPU region violation exceptions:
•
MPU region violation (instruction)—Any instruction fetch can cause this exception.
•
MPU region violation (data)—Load, store,
cause this exception.
The general exception handler can inspect the
which kind of MPU region violation exception occurred.
3.7.8. Other Exceptions
The preceding sections describe all of the exception types defined by the Nios II
architecture at the time of publishing. However, some processor implementations
might generate exceptions that do not fall into the categories listed in the preceding
sections. Therefore, a robust exception handler must provide a safe response (such as
issuing a warning) in the event that it cannot identify the cause of an exception.
3.7.9. Exception Processing Flow
Except for the break exception (refer to the Processing a Break section of this
chapter), this section describes how the processor responds to exceptions, including
interrupts and instruction-related exceptions.
Nios II Processor Reference Guide
88
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NII-PRG | 2018.04.18
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