Table of Contents
Advertisement
8.5.56. ldh / ldhio
Instruction
Operation
Assembler Syntax
Example
Description
Usage
Exceptions
Instruction Type
Instruction Fields
Table 102.
ldh
31
30
29
A
15
14
13
Table 103.
ldhio
31
30
29
A
15
14
13
Nios II Processor Reference Guide
208
28
27
26
25
12
11
10
9
IMM16
28
27
26
25
12
11
10
9
IMM16
load halfword from memory or I/O peripheral
rB
σ(Mem16[rA + σ(IMM16)])
ldh rB, byte_offset(rA)
ldhio rB, byte_offset(rA)
ldh r6, 100(r5)
Computes the effective byte address specified by the sum of
rA and the instruction's signed 16-bit immediate value.
Loads register rB with the memory halfword located at the
effective byte address, sign extending the 16-bit value to 32
bits. The effective byte address must be halfword aligned. If
the byte address is not a multiple of 2, the operation is
undefined.
In processors with a data cache, this instruction may
retrieve the desired data from the cache instead of from
memory. Use the
ldhio
processors with a data cache,
and is guaranteed to generate an Avalon-MM data transfer.
In processors without a data cache,
For more information on data cache, refer to the Cache and
Tightly Coupled Memory chapter of the Nios II Software
Developer's Handbook.
Supervisor-only data address
Misaligned data address
TLB permission violation (read)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
I
= Register index of operand rA
A
= Register index of operand rB
B
= 16-bit signed immediate value
IMM16
Bit Fields
24
23
22
21
B
8
7
6
5
Bit Fields
24
23
22
21
B
8
7
6
5
8. Instruction Set Reference
NII-PRG | 2018.04.18
instruction for peripheral I/O. In
bypasses the cache
ldhio
acts like
ldhio
ldh
20
19
18
17
IMM16
4
3
2
1
0x0f
20
19
18
17
IMM16
4
3
2
1
0x2f
.
16
0
16
0
Advertisement
Table of Contents
