User Pmod Gpio Headers - Xilinx KCU116 User Manual

Table 3‐20: KCU116 GPIO Connections to FPGA U1 (Cont'd)
FPGA Pin (U1)
BANK 86
4-Pole DIP SW (active-High)
BANK 86
BANK 86
BANK 86
BANK 86
CPU Reset Pushbutton (active-High)
BANK 86

User Pmod GPIO Headers

[Figure 2-1, callout 28]
The KCU116 evaluation board supports two Pmod GPIO headers J55 and J87. The Pmod nets
are connected to FPGA U1 Bank 87. Pmod connector J55 is a right-angle receptacle and
connector J87 is a vertical male pin header.
Figure 3-25 shows the GPIO Pmod headers J55 and J87.
X-Ref Target - Figure 3-25
Figure 3‐25: Pmod Connectors J52 and J53 with Level Shifters U41 and U42
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
Schematic Net
Name
A9 GPIO_SW_C
G11 GPIO_DIP_SW0
H11 GPIO_DIP_SW1
H9 GPIO_DIP_SW2
J9 GPIO_DIP_SW3
B9 CPU_RESET
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Chapter 3: Board Component Descriptions
I/O Standard
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
Send Feedback
GPIO
SW15.3
SW13.1
SW13.2
SW13.3
SW13.4
SW17.3
X18536-042017
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