User Ps Switches; User Pmod Gpio Headers - Xilinx ZC702 User Manual

User PS Switches

[Figure 1-2, near callout 18]
Figure 1-25 shows the user PS pushbutton and DIP switch circuit.
X-Ref Target - Figure 1-24
PS_DIP_SW0
PS_DIP_SW1
Table 1-26 lists the user PS-side pushbutton and DIP switch connections to XC7Z020 SoC
U1 Bank 500.
Table 1-26: User PS Switch Connections to XC7Z020 SoC U1
XC7Z020 SoC (U1) Pin

User PMOD GPIO Headers

[Figure 1-2, callout 28]
The ZC702 board supports two GPIO headers J62 and J63. The PMOD nets connected to
these headers are dual-purpose, with the
J63 has a second dual-purpose function. The even numbered pins are wired in parallel to
the Arm PJTAG header J41 pins TDI, TIMS, TCK, and TDO. The J41 PJTAG signals are
connected to SoC Bank 13 GPIO pins which simultaneously drive J41 and J63. When J41 is
used for Arm PJTAG functionality, the J63 even numbered pin should not be used. When J63
even numbered pins are used as GPIO, connector J41 should not be used.
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
VCCMIO_PS (1.8V)
SW13
4
3
R413
4.7 kΩ
0.1 Ω
5%
GND
Figure 1-24: User PS Pushbutton and DIP Switch Circuit
B6 PS_DIP_SW0
C5 PS_DIP_SW1
www.xilinx.com
1
2
GND
Net Name Switch and Pin Reference
SW13.4 and SW15.1
SW14.4 and SW15.2
User LEDs wired in parallel to the header pins.
Feature Descriptions
VCCMIO_PS (1.8V)
SW14
4 1
3 2
R414
4.7 kΩ
0.1 Ω
5%2719
VCCMIO_PS (1.8V)
SW15
1 4
2 3
SDA02H1SBD
UG850_c1_24_032719
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