User Push Buttons (Active High); Fpga U1 User Gpio Header; Fpga U1 Usb To Uart Bridge - Xilinx ML630 User Manual

User Push Buttons (Active High)

Figure 1-2
SW4, SW6, SW8 and SW9 are active-High user pushbuttons that are connected to user I/O
pins on FPGA U1 as shown in
determined by the user.
Table 1-5: FPGA U1 User Pushbuttons

FPGA U1 User GPIO Header

Figure 1-2
A standard 2 x 6, 100-mil pitch header (J285) brings out six FPGA I/Os for test purposes.
Table 1-6
Table 1-6: FPGA U1 User GPIO Header J285

FPGA U1 USB to UART Bridge

Figure 1-2
Communications between the ML630 board FPGA U1 and a host computer are
accomplished through a USB cable connected to J54. Control is provided by U26, a USB to
UART bridge (Silicon Laboratories CP2103).
for the USB connector J54.
Table 1-7: : J54 USB Mini-B Connector Pin Assignments and Signals
ML630 Board User Guide
UG828 (v1.0) September 28, 2011
callout [22]
FPGA U1 Pin Net Name
H26 U1_USER_PB1
J26 U1_USER_PB2
N24 U1_USER_PB3
N23 U1_USER_PB4
callout [23]
lists these pins. J285 odd pin numbers are wired to GND (ground).
FPGA U1 Pin Net Name
J35 U1_USER_IO_1
K35 U1_USER_IO_2
D35 U1_USER_IO_3
E35 U1_USER_IO_4
P35 U1_USER_IO_5
P34 U1_USER_IO_6
callout [24]
J54 Pin Signal Name
1 VBUS
2 U1_USB_D_N
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Table 1-5. These switches can be used for any purpose
Reference
Designator
SW4
SW6
SW8
SW9
J285 Pin
2
4
6
8
10
12
Table 1-7 lists the pin assignments and signals
+5V from host system
Bidirectional differential serial data (N-side)
Detailed Description
Description
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