Fpga Mezzanine Card Interface; Fmc Hpc Connector J5 - Xilinx KCU116 User Manual

FPGA Mezzanine Card Interface

[Figure 2-1, callout 34]
The KCU116 evaluation board supports the VITA 57.1 FPGA mezzanine card (FMC)
specification by providing a subset implementation of the high pin count (HPC) connector
at J5. The FMC connector uses a 10 x 40 form factor. The HPC connector is populated with
400 pins. The connector is keyed so that the mezzanine card faces away from the board
when installed on the KCU116 evaluation board.
The connector type is the Samtec SEAF Series, 1.27 mm (0.050 in) pitch, which mates with
the SEAM series connector. For more information about the SEAF series connectors, see the
Samtec website
the VITA FMC Marketing Alliance website

FMC HPC Connector J5

[Figure 2-1, callout 34]
The 400 pin HPC connector defined by the FMC specification
connectivity for up to:
• 160 single-ended or 80 differential user-defined signals
• 10 GT transceivers
• 2 GT clocks
• 4 differential clocks
• 159 ground and 15 power connections
The HPC0 connector at J5 implements a subset of the full FMC HPC connectivity:
• 46 single-ended or 23 differential signal pairs (23 LA pairs: LA[00:22])
• 4 GTY transceivers
• 2 GTY clocks
• 1 differential clock
• 159 ground and 11 power connections
The KCU116 board FMC VADJ voltage VADJ_FMC for the J5 FMC connector is determined by
the MAX15301 U63 voltage regulator described in
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
[Ref 32]. For more information about the VITA 57.1 FMC specification, see
www.xilinx.com
Chapter 3: Board Component Descriptions
[Ref 33].
(Figure
KCU116 Board Power
A-1) provides
System.
68
Send Feedback