Fpga Mezzanine Card Interface - Xilinx AC701 User Manual

Chapter 1: AC701 Evaluation Board Features
Configuration Mode Switch SW1
The AC701 board supports two of the five 7 series FPGA configuration modes:
•
•
Each configuration interface corresponds to one or more configuration modes and bus
widths as listed in
2, and 3 respectively as shown in
Note:
X-Ref Target - Figure 1-40
The default mode setting is M[2:0] = 001, which selects Master SPI at board power-on.
Table 1-25: AC701 Board FPGA Configuration Modes
See UG470, 7 Series FPGAs Configuration User Guide for further details on configuring the
7 series FPGAs.

FPGA Mezzanine Card Interface

[Figure
The AC701 board supports the VITA 57.1 FPGA Mezzanine Card (FMC) specification by
providing high pin count (HPC) connector J30. HPC J30 is keyed so that a the mezzanine
card faces away from the AC701 board when connected.
Signaling Speed Ratings:
•
•
•
•
56
Master SPI using the on-board Quad SPI flash memory
JTAG using a standard-A to micro-B USB cable for connecting the host PC to the
AC701 board configuration port (via Digilent module)
Table 1-25. The mode switches M2, M1, and M0 are on SW1 positions 1,
On the AC701 board, SW1 switch position 2 is not used.
FPGA_M2
FPGA_M1
FPGA_M0
SW13 DIP Switch
Configuration Mode
Settings (M[2:0])
Master SPI
JTAG
1-2, callout 29]
Single-ended: 9 GHz (18 Gb/s)
Differential Optimal Vertical: 9 GHz (18 Gb/s)
Differential Optimal Horizontal: 16 GHz (32 Gb/s)
High Density Vertical: 7 GHz (15 Gb/s)
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Figure 1-40.
R339 R338 R337
1.21K 1% 1.21K 1% 1.21K 1%
1/10W 1/10W 1/10W
Figure 1-40: Mode Switch SW1
Bus Width
001
101
FPGA_3V3
SW1
1 6
NC 2 5
3 4
SDA03H1SBD
UG952_c1_36_011713
CCLK Direction
x1, x2, x4 Output
x1 Not Applicable
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013