Fpga Mezzanine Card Hpc Interface - Xilinx Kintex-7 FPGA KC724 User Manual

The bridge device also provides as many as 4 GPIO signals that can be defined for status
and control information
Table 1-16: CP2103 USB-to-UART Bridge User GPIO
FPGA (U1)
Pin Function
L17 SelectIO™
H19 SelectIO
J19 SelectIO
H17 SelectIO
A royalty-free software driver named Virtual COM Port (VCP) is available from Silicon
Laboratories. This driver permits the CP2103 USB-to-UART bridge to appear as a COM
port to the host computer communications application software (for example,
HyperTerminal or TeraTerm). The VCP driver must be installed on the host computer prior
to establishing communications with the KC724 board.

FPGA Mezzanine Card HPC Interface

Callout
The KC724 board features two high pin count (HPC) connectors as defined by the VITA
57.1 FPGA Mezzanine card (FMC) specification. The FMC HPC connector is a 10 x 40
position socket. See
of signal names to pin coordinates.
FMC1 HPC connector provides connectivity for:
•
•
FMC2 HPC connector JA3 provides connectivity for:
•
•
Note:
the FPGA banks that each FMC interface maps to. FMC1 tracks VCCO_HP. FMC2 tracks VCCO_HR.
KC724 GTX Transceiver Characterization Board
UG932 (v2.2) October 10, 2014
(Table
Direction IOSTANDARD
In/Out LVCMOS18
In/Out LVCMOS18
In/Out LVCMOS18
In/Out LVCMOS18
29 and 30, Figure 1-2.
Appendix C, VITA 57.1 FMC Connector Pinouts
69 differential user defined pairs:
• 34 LA pairs
• 18 HA pairs
• 17 HB pairs
2 differential clocks
80 differential user defined pairs:
• 34 LA pairs
• 24 HA pairs
• 22 HB pairs
4 differential clocks
The V voltage for the FMC HPC connectors on the KC724 board tracks the I/O voltage of
ADJ
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1-16).
Schematic Net
Name
USB_GPIO_0
USB_GPIO_1
USB_GPIO_2
USB_GPIO_3
Detailed Description
Device (U34)
Pin Function Direction
19 GPIO In/Out
18 GPIO In/Out
17 GPIO In/Out
16 GPIO In/Out
for a cross-reference
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