Fpga Mezzanine Card Interface; Fmc Lpc Connector J5 - Xilinx ZCU104 User Manual

Table 3-28: PS-GTR Bank 505 Interface Connections (Cont'd)
XCZU7EV
XCZU7EV Pin Name
(U1) Pin
P27 PS_MGTREFCLK1P
P28 PS_MGTREFCLK1N
M27 PS_MGTREFCLK2P
M28 PS_MGTREFCLK2N
M31 PS_MGTREFCLK3P
M32 PS_MGTREFCLK3N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.

FPGA Mezzanine Card Interface

[Figure 2-1, callout 25]
The ZCU104 evaluation board supports the VITA 57.1 FPGA mezzanine card (FMC)
specification [Ref 19]
form factor, partially populated with 160 pins. The connector is keyed so that a mezzanine
card, when installed in the FMC LPC connector on the ZCU104 evaluation board, faces away
from the board

FMC LPC Connector J5

[Figure 2-1, callout 25]
The FMC connector at J5 implements the full FMC LPC connectivity:
• 68 single-ended, or 34 differential user-defined pairs (34 LA pairs: LA[00:33])
• One GTH transceiver DP differential pair
• Two GBTCLK differential clocks
• 61 ground and 10 power connections
The ZCU104 board FMC VADJ voltage for LPC connector J5 is determined by the
IRPS5401MTRPBF U180 voltage regulator described in
values for the VADJ_FMC rail are 1.2V, 1.5V, and 1.8V. The LPC J5 connections to XCZU7EV
U1 are shown in
ZCU104 Board User Guide
UG1267 (v1.1) October 9, 2018
Schematic Net Name
GTR_REF_CLK_SATA_C_P
GTR_REF_CLK_SATA_C_N
GTR_REF_CLK_USB3_C_P
GTR_REF_CLK_USB3_C_N
GTR_REF_CLK_DP_C_P
GTR_REF_CLK_DP_C_N
by implementing the LPC connector (J5). LPC connectors use a 10 x 40
Table 3-29 and Table 3-30.
www.xilinx.com
Chapter 3: Board Component Descriptions
Connected To
(2)
Pin No. Pin Name
(1)
37 Q5
(1)
36 NQ5
(1)
27 Q2
(1)
28 NQ2
(1)
23 Q3
(1)
23 NQ3
Board Power System, page
Device
8T49N287 U182
83. Valid
76
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