Fpga Mezzanine Card Interface - Xilinx AC701 User Manual

X-Ref Target - Figure 1-36
The default mode setting is M[2:0] = 001, which selects Master SPI at board power-on.
Table 1-25: AC701 Board FPGA Configuration Modes
See UG470, 7 Series FPGAs Configuration User Guide for further details on configuring the 7
series FPGAs.

FPGA Mezzanine Card Interface

[Figure
The AC701 board supports the VITA 57.1 FPGA Mezzanine Card (FMC) specification by
providing high pin count (HPC) connector J30. HPC J30 is keyed so that a the mezzanine
card faces away from the AC701 board when connected.
Signaling Speed Ratings:
•
•
•
•
The Samtec connector system is rated for signaling speeds up to 9 GHz (18 Gb/s) based on
a -3 dB insertion loss point within a two-level signaling environment.
Connector Type:
•
For more information about SEAF series connectors, go to the Samtec website at:
www.samtec.com.
HPC Connector J30
[Figure
AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
FPGA_M2
FPGA_M1
FPGA_M0
SW13 DIP Switch
Configuration Mode
Settings (M[2:0])
Master SPI
JTAG
1-2, callout 29]
Single-ended: 9 GHz (18 Gb/s)
Differential Optimal Vertical: 9 GHz (18 Gb/s)
Differential Optimal Horizontal: 16 GHz (32 Gb/s)
High Density Vertical: 7 GHz (15 Gb/s)
Samtec SEAF Series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector
1-2, callout 29]
www.xilinx.com
R339 R338 R337
1.21K 1% 1.21K 1% 1.21K 1%
1/10W 1/10W 1/10W
Figure 1-36: Mode Switch SW1
Bus Width
001
101
Feature Descriptions
FPGA_3V3
SW1
1 6
2 5
3 4
SDA03H1SBD
UG952_c1_03_100212
CCLK Direction
x1, x2, x4 Output
x1 Not Applicable
55