Processor Information In The Core I/O Area; Vector Table Base Register (Ttbr, 0Xffff80); Processor Id Register (Idir, 0Xffff84); Debug Ram Base Register (Dbram, 0Xffff90) - Epson S1C17 Series Manual

4 ADDRESS MAP

4.2 Processor Information in the Core I/O Area

The reserved core I/O area contains the processor information described below.

4.2.1 Vector Table Base Register (TTBR, 0xffff80)

Register name Address Bit
Vector table FFFF80
D31–24
base register (L)
D23
|
D0
This is a read-only register that contains the vector table base address.
The vector table contains the vectors to the interrupt handler routines (handler routine start address) that will be
read by the S1C17 Core to execute the handler when an interrupt occurs. The boot address from which the program
starts running after a reset must be written to the top of the vector table.
Refer to the Technical Manual of each model for the address stored in this register.

4.2.2 Processor ID Register (IDIR, 0xffff84)

Register name Address Bit
Processor ID FFFF84 D7
register (B) |
D0
This is a read-only register that contains the ID code to represent a processor model. The S1C17 Core's ID code is
0x10.

4.2.3 Debug RAM Base Register (DBRAM, 0xffff90)

Register name Address Bit
Debug RAM FFFF90
D31–24
base register (L) D23
|
D0
This is a read-only register that contains the start address of a work area (64 bytes) for debugging.
Refer to the Technical Manual of each model for the address stored in this register.
* In addition to the above registers, the reserved core I/O area contains some registers for debugging. For the debug
registers, refer to Section 6.5, "Debug Circuit."
4-2
Name Function
–
Unused (fixed at 0)
TTBR23
Vector table base address
|
TTBR[7:0] is fixed at 0x0.
TTBR0
Name Function
IDIR7 Processor ID
| 0x10: S1C17 Core
IDIR0
Name Function
–
Unused (fixed at 0)
DBRAM23 Debug RAM base address
| DBRAM[5:0] is fixed at 0x0.
DBRAM0
Seiko Epson Corporation
Setting Init. R/W
0x0 0x0 R
*
0x0–0xFFFB00 R
(256 byte units)
Setting Init. R/W
0x10 0x10 R
Setting Init. R/W
0x0 0x0 R
0x0–0xFFFDC0 * R
(64 byte units)
S1C17 CORE MANUAL
Remarks
Initial value is set by
the TTBR pins of the
C17 macro.
Remarks
Remarks
Initial value is set in
the C17 RTL-define
DBRAM_BASE.
(REV. 1.2)