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Peripheral circuit
DMA controller (DMAC)
4.5.1 System-Protect Function
The system-protect function protects control registers and bits from writings. They cannot be rewritten unless write
protection is removed by writing 0x0096 to the SYSPROT.PROT[15:0] bits. This function is provided to prevent
deadlock that may occur when a system-related register is altered by a runaway CPU. See "Control Registers" in
each peripheral circuit to identify the registers and bits with write protection.
Note: Once write protection is removed using the SYSPROT.PROT[15:0] bits, write enabled status is
maintained until write protection is applied again. After the registers/bits required have been al-
tered, apply write protection.
4.6 Instruction Cache
This IC includes an instruction cache. Enabling the cache function translates into reduced current consumption, as
the Flash memory access frequency is decreased.
This function is enabled by setting the CACHECTL.CACHEEN bit to 1. Setting this bit to 0 clears the instruction
codes stored in the cache.
Before placing the IC into SLEEP or HALT mode, disable the cache function by setting the CACHECTL.
CACHEEN bit to 0.
4.7 Memory Mapped Access Area For External Flash Memory
This area is used to read data from the external Flash memory via the quad synchronous serial interface. For more
information, refer to the "Quad Synchronous Serial Interface" chapter.
4.8 Control Registers
System Protect Register
Register name
Bit
SYSPROT
15–0 PROT[15:0]
Bits 15–0 PROT[15:0]
These bits protect the control registers related to the system against writings.
0x0096 (R/W):
Other than 0x0096 (R/W): Enable system protection
While the system protection is enabled, any data will not be written to the affected control bits (bits
with "WP" or "R/WP" appearing in the R/W column).
CACHE Control Register
Register name
Bit
CACHECTL
15–8 –
7–2 –
1
0
Bits 15–1 Reserved
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
Address
0x0020 103c DMACPRCLR
0x0020 104c DMACERRIF
0x0020 2000 DMACENDIF
0x0020 2008 DMACENDIESET
0x0020 200c DMACENDIECLR
0x0020 2010 DMACERRIESET
0x0020 2014 DMACERRIECLR
Bit name
Initial
0x0000
Disable system protection
Bit name
Initial
0x00
0x00
–
CACHEEN
Seiko Epson Corporation
Register name
DMAC Priority Clear Register
DMAC Error Interrupt Flag Register
DMAC Transfer Completion Interrupt Flag Register
DMAC Transfer Completion Interrupt Enable Set Register
DMAC Transfer Completion Interrupt Enable Clear Register
DMAC Error Interrupt Enable Set Register
DMAC Error Interrupt Enable Clear Register
Reset
R/W
H0
R/W
–
Reset
R/W
–
R
–
–
R
1
–
R
0
H0
R/W
4 MEMORY AND BUS
Remarks
Remarks
4-9
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