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3 CPU AND DEBUGGER
3.2 CPU Core
3.2.1 CPU Registers
The CPU includes eight general-purpose registers and three special registers (Table 3.2.1.1).
CPU register name
General-purpose registers
Special
Program counter
registers
Stack pointer
Processor status register
For details on the CPU registers, refer to the "S1C17 Family S1C17 Core Manual." For more information on the
reset vector, refer to the "Interrupt Controller" chapter.
3.2.2 Instruction Set
The CPU instruction codes are all fixed to 16 bits in length which, combined with pipelined processing, allows the
most important instructions to be executed in one cycle. For details on the instructions, refer to the "S1C17 Family
S1C17 Core Manual."
3.2.3 Reading PSR
The PSR contents can be read through the MSCPSR register. Note, however, that data cannot be written to PSR
through the MSCPSR register.
3.2.4 I/O Area Reserved for the S1C17 Core
The address range from 0xfffc00 to 0xffffff is the I/O area reserved for the S1C17 core. Do not access this area ex-
cept when it is required.
3.3 Debugger
3.3.1 Debugging Functions
The debugger provides the following functions:
• Instruction break: A debug interrupt is generated immediately before the set instruction address is executed. An
instruction break can be set at up to four addresses.
• Single step:
A debug interrupt is generated after each instruction has been executed.
• Forcible break:
A debug interrupt is generated using an external input signal.
• Software break: A debug interrupt is generated when the brk instruction is executed.
When a debug interrupt occurs, the CPU enters DEBUG mode. The peripheral circuit operations in DEBUG mode
depend on the setting of the DBRUN bit provided in the clock control register of each peripheral circuit. For more
information on the DBRUN bit, refer to "Clock Supply in DEBUG Mode" in each peripheral circuit chapter. DE-
BUG mode continues until a cancel command is sent from the personal computer or the CPU executes the retd in-
struction. Neither hardware interrupts nor NMI are accepted during DEBUG mode.
3-2
Table 3.2.1.1 Initialization of CPU Registers
R0 to R7
0x000000
PC
The reset vector is automatically loaded.
SP
0x000000
PSR
0x00
Seiko Epson Corporation
Initial
S1C17W12/W13 TECHNICAL MANUAL
Reset
H0
H0
H0
H0
(Rev. 1.2)
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