Table of Contents
Advertisement
12 UART (UART)
12.1 Overview
The UART is an asynchronous serial interface. The features of the UART are listed below.
• Includes a baud rate generator for generating the transfer clock.
• Supports 7- and 8-bit data length (LSB first).
• Odd parity, even parity, or non-parity mode is selectable.
• The start bit length is fixed at 1 bit.
• The stop bit length is selectable from 1 bit and 2 bits.
• Supports full-duplex communications.
• Includes a 2-byte receive data buffer and a 1-byte transmit data buffer.
• Includes an RZI modulator/demodulator circuit to support IrDA 1.0-compatible infrared communications.
• Can detect parity error, framing error, and overrun error.
• Can generate receive buffer full (1 byte/2 bytes), transmit buffer empty, end of transmission, parity error, framing
error, and overrun error interrupts.
• Input pin can be pulled up with an internal resistor.
• The output pin is configurable as an open-drain output.
Figure 12.1.1 shows the UART configuration.
Item
Number of channels
UART Ch.n
Clock generator
Interrupt
controller
S1C17W03/W04 TECHNICAL MANUAL
(Rev. 1.2)
Table 12.1.1 UART Channel Configuration of S1C17W03/W04
32-pin package
CLK_UARTn
CLKSRC[1:0]
CLKDIV[1:0]
DBRUN
MODEN
Receive data buffer
RXD[7:0]
Transmit data buffer
TXD[7:0]
TENDIE
FEIE
PEIE
OEIE
RB2FIE
RB1FIE
TBEIE
Figure 12.1.1 UART Configuration
Seiko Epson Corporation
2 channels (Ch.0 and Ch.1)
Baud rate
generator
Transmit/receive
control circuit
Shift register
RZI demodulator
Shift register
RZI modulator
Interrupt
control circuit
12 UART (UART)
48-pin package/chip
BRT[7:0]
FMD[3:0]
CHLN
PREN
PRMD
STPB
RBSY
TBSY
SFTRST
PUEN
USINn
INVIRRX
USOUTn
INVIRTX
IRMD
OUTMD
TENDIF
FEIF
PEIF
OEIF
RB2FIF
RB1FIF
TBEIF
12-1
Advertisement
Table of Contents
