Chapter 3: Dsp48E1 Design Considerations; Designing For Performance; Designing For Power - Xilinx 7 Series User Manual

DSP48E1 Design Considerations
This chapter describes some design features and techniques to use to achieve higher
performance, lower power, and lower resources in a particular design.
This chapter contains the following sections:
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Designing for Performance

To achieve maximum performance when using the DSP48E1 slice, the design needs to be
fully pipelined. For multiplier-based designs, the DSP48E1 slice requires a three-stage
pipeline. For non-multiplier-based designs, a two-stage pipeline should be used. Also see
the 7 series FPGA data sheets
two registers can be used within the DSP48E1 slice, always use the M register.

Designing for Power

The USE_MULT attribute selects usage of the multiplier. This attribute should be set to
NONE to save power when using only the Adder/Logic Unit. Functions implemented in
the DSP48E1 slice use less power than those implemented in fabric. Using the cascade
paths within the DSP48E1 slice instead of fabric routing is another way to reduce power. A
multiplier with the M register turned on uses less power than one where the M register is
not used. For operands less than 25 x 18, fabric power can be reduced by placing operands
into the MSBs and zero padding unused LSBs.
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018
Designing for Performance
Designing for Power
Adder Tree Versus Adder Cascade
Connecting DSP48E1 Slices across Columns
Time Multiplexing the DSP48E1 Slice
Miscellaneous Notes and Suggestions
Pre-Adder Block Applications
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[Ref 6]. If latency is important in the design and only one or
Chapter 3
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