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User Guide
LTC9101-3 EVALUATION KIT
Table 2. Default PoE Operation vs. port LEDs
LED
Condition
Port Status
Detect Open
Off
Port Powered
On
Detect Invalid
Off
Class Invalid
Off
Inrush Fault
Off
P
, I
and I
Off
CUT
CUT
LIM
DC Disconnect
Off
Power Denied
Blink
Power Revoked
Blink
NOTE: Blink rate is 800ms on and 800ms off.
DEVICE CONFIGURATION
The CFG1 pin state during reset configures the number of analog
controllers in the system. The CFG1 pin connects to a jumper that
pulls either HI for a logical 1, or LO for logical 0. See
the numbers of ports and LTC9103s set by CFG1 pin. CFG1 pin
also sets the default system power budget and near-limit warning
thresholds. See
Power Management
The CFG0 and CFG2 jumpers must be set LO, to set the CFG0 and
CFG2 pins to a logical 0.
CUSTOM CONFIGURATIONS
An
LTC9101-3/LTC9103
system may be configured in a variety of
ways by storing a custom configuration package in a dedicated
flash partition. If a stored configuration is utilized, CFG1 is still
required to inform the LTC9101-3 how many analog controllers
are in the system. Refer to the data sheet for more information
and contact ADI Applications for assistance with generating custom
configuration packages.
DIGITAL CONNECTIONS
2
The DC590 USB to I
C controller board is connected to the EVAL-
LTC9101-3-MB-AZ motherboard at J1 through a 14-pin ribbon
2
cable. The LTC9101-3's I
C base address is 0x20. SDAOUT and
SDAIN can be tied together through a shunt resistor, R73. Turrets
on the EVAL-LTC9101-3-MB-AZ motherboard provide test points for
SCL, SDAIN, SDAOUT, V
, DGND, and RESET.
DD
RESET PUSHBUTTON
Pushbutton switch SW1, when pressed, pulls the RESET pin of the
daughter card logic low. The PSE controller is then held inactive
with all ports off. When SW1 is released, RESET is pulled high, and
the PSE returns to autonomous operation while OVR, Status, and
Fault LEDs run through the LED power on self test.
analog.com
Port Fault
Off
Off
Blink
Blink
Blink
Blink
Blink
Off
Off
Table 1
for
section for more information.
EVAL-LTC9101-3
ONBOARD 3.3 V SUPPLY
The EVAL-LTC9101-3-MB-AZ motherboard has an onboard (non-
isolated) 3.3 V/1 A buck regulator that provides a local 3.3 V,
with the net named BUCK33. This onboard logic supply is for
demonstration purposes only and allows for use of a single supply
while evaluating the EVAL-LTC9101-3.
SURGE TESTING
The EVAL-LTC9101-3 can be configured with either the Digital
domain connected to reference ground plane, or with the Digital do-
main floating with the Analog domain for different surge test setups.
The default EVAL-LTC9101-3 configuration has DGND connected
to V
and floating from chassis ground.
EE
LEGACY MODE
Legacy Mode operation is enabled with the LEGACY pin, which is
controlled by the LEGACY jumper (JP15). If the LEGACY jumper
is LO, Legacy mode is enabled and legacy PDs with large common-
mode capacitance (>10 μF) will be powered. If the LEGACY jumper
is HI or floating, legacy mode is disabled and only valid IEEE
802.3 PDs will be powered. The LEGACY pin state is continuously
monitored.
Rev. 0 | 8 of 10
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