Page 1 AM1802 ARM Microprocessor System Reference Guide Literature Number: SPRUGX5A May 2011...
Page 3: Table Of Contents
5.2.6 Invalid Accesses and Exceptions .................... 5.2.7 Reset Considerations ....................5.2.8 Interrupt Support ..................5.2.9 Emulation Considerations ......................MPU Registers ..............5.3.1 Revision Identification Register (REVID) SPRUGX5A – May 2011 Contents Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 4 7.3.20 PLLC0 Divider 7 Register (PLLDIV7) ............. 7.3.21 PLLC0 Oscillator Divider 1 Register (OSCDIV) ............. 7.3.22 PLLC1 Oscillator Divider 1 Register (OSCDIV) .............. 7.3.23 PLL Post-Divider Control Register (POSTDIV) SPRUGX5A – May 2011 Contents Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 5 8.6.19 PSC1 Module Control n Register (modules 0-31) (MDCTLn) ......................Power Management ....................... Introduction ..................Power Consumption Overview ....................PSC and PLLC Overview ........................Features ...................... Clock Management SPRUGX5A – May 2011 Contents Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 6 ............10.4.21 Pullup/Pulldown Enable Register (PUPD_ENA) ............10.4.22 Pullup/Pulldown Select Register (PUPD_SEL) ..............10.4.23 RXACTIVE Control Register (RXACTIVE) ..................ARM Interrupt Controller (AINTC) ....................... 11.1 Introduction SPRUGX5A – May 2011 Contents Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 7 11.4.37 Host Interrupt Enable Register (HIER) ........... 11.4.38 Host Interrupt Prioritized Vector Register 1 (HIPVR1) ........... 11.4.39 Host Interrupt Prioritized Vector Register 2 (HIPVR2) ......................Boot Considerations SPRUGX5A – May 2011 Contents Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 9 List of Figures ................ 1-1. AM1802 ARM Microprocessor Block Diagram ..................3-1. System Interconnect Block Diagram ....................... 5-1. MPU Block Diagram ......................5-2. Permission Fields ................... 5-3. Revision ID Register (REVID) ..................5-4. Configuration Register (CONFIG) ..............5-5. Interrupt Raw Status/Set Register (IRAWSTAT) ..............
Page 10 10-8. Interrupt Enable Status/Clear Register (IENSTAT) ................... 10-9. Interrupt Enable Register (IENSET) ................10-10. Interrupt Enable Clear Register (IENCLR) ..................10-11. End of Interrupt Register (EOI) SPRUGX5A – May 2011 List of Figures Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 11 11-8. System Interrupt Status Indexed Clear Register (SICR) ............. 11-9. System Interrupt Enable Indexed Set Register (EISR) ............11-10. System Interrupt Enable Indexed Clear Register (EICR) SPRUGX5A – May 2011 List of Figures Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 12 11-39. Host Interrupt Enable Register (HIER) .............. 11-40. Host Interrupt Prioritized Vector Register 1 (HIPVR1) .............. 11-41. Host Interrupt Prioritized Vector Register 2 (HIPVR2) SPRUGX5A – May 2011 List of Figures Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 13 List of Tables ..................2-1. Exception Vector Table for ARM ................2-2. Different Address Types in ARM System ............3-1. AM1802 ARM Microprocessor System Interconnect Matrix ....................5-1. MPU Memory Regions ....................5-2. MPU Default Configuration ....................5-3. Device Master Settings ..................
Page 14 8-21. Power Domain 1 Configuration Register (PDCFG1) Field Descriptions ............8-22. Module Status n Register (MDSTATn) Field Descriptions ..........8-23. PSC0 Module Control n Register (MDCTLn) Field Descriptions SPRUGX5A – May 2011 List of Tables Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 15 10-45. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions ........... 10-46. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions ........... 10-47. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions SPRUGX5A – May 2011 List of Tables Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 16 11-39. Host Interrupt Enable Register (HIER) Field Descriptions ........11-40. Host Interrupt Prioritized Vector Register 1 (HIPVR1) Field Descriptions ........11-41. Host Interrupt Prioritized Vector Register 2 (HIPVR2) Field Descriptions SPRUGX5A – May 2011 List of Tables Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 19: Preface
C6000 DSP product folder at: www.ti.com/c6000. SPRUFU0 — AM17x/AM18x ARM Microprocessors Peripherals Overview Reference Guide. Provides an overview and briefly describes the peripherals available on the AM17x/AM18x ARM Microprocessors. SPRUGX5A – May 2011 Read This First Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 21: Overview
Chapter 1 SPRUGX5A – May 2011 Overview ........................... Topic Page ...................... Introduction ....................Block Diagram ....................ARM Subsystem SPRUGX5A – May 2011 Overview Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 22: Introduction
Introduction www.ti.com Introduction The AM1802 ARM microprocessor contains an ARM RISC CPU for general-purpose processing and systems control. The AM1802 ARM microprocessor consists of the following primary components: • ARM926 RISC CPU core and associated memories • A set of I/O peripherals •...
Page 23: Arm Subsystem
...................... Introduction ..................Operating States/Modes ................Processor Status Registers ..............Exceptions and Exception Vectors ................. The 16-BIS/32-BIS Concept .................. 16-BIS/32-BIS Advantages ..................Co-Processor 15 (CP15) SPRUGX5A – May 2011 ARM Subsystem Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 24: Introduction
RAM (typically used for vector table) and 64 KB ROM (for boot images) associated with it. The RAM/ROM locations are not accessible by any other master peripherals. Furthermore, the ARM has DMA and CFG bus master ports via the AHB interface. SPRUGX5A – May 2011 ARM Subsystem Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 25: Operating States/Modes
Bit 28 - V bit: Overflow or underflow NOTE: See the Programmer’s Model of the ARM926EJ-S Technical Reference Manual (TRM), downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information. SPRUGX5A – May 2011 ARM Subsystem Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 26: Exceptions And Exception Vectors
F Bit State on Entry Reset Supervisor Undefined instruction Undefined Unchanged Software interrupt Supervisor Unchanged Pre-fetch abort Abort Unchanged Data abort Abort Unchanged Reserved — — — Unchanged SPRUGX5A – May 2011 ARM Subsystem Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 27: The 16-Bis/32-Bis Concept
Various portions of a system can be optimized for speed or for code density by switching between 16-BIS and 32-BIS execution, as appropriate. SPRUGX5A – May 2011 ARM Subsystem Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 28: Co-Processor 15 (Cp15)
Lockdown of TLB entries, using CP15 register 10 NOTE: See the Memory Management Unit of the ARM926EJ-S Technical Reference Manual (TRM), downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information. SPRUGX5A – May 2011 ARM Subsystem Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 29: Caches And Write Buffer
NOTE: See the Caches and Write Buffer of the ARM926EJ-S Technical Reference Manual (TRM), downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information. SPRUGX5A – May 2011 ARM Subsystem Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 31: System Interconnect
Chapter 3 SPRUGX5A – May 2011 System Interconnect ........................... Topic Page ...................... Introduction ..............System Interconnect Block Diagram SPRUGX5A – May 2011 System Interconnect Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 32: Introduction
The system master peripherals include the ARM, the EDMA3 transfer controllers, EMAC, and USB2.0. Not all master peripherals may connect to all slave peripherals. The supported connections are designated by an X in Table 3-1. Table 3-1. AM1802 ARM Microprocessor System Interconnect Matrix Masters Slaves Default ROM,...
Page 33: System Interconnect Block Diagram
EDMA3_0_TC0 IP Module EDMA3_0_TC1 Synchronous Bridge Timer64P2 Asynchronous Bridge BR F5 SCR F8 Timer64P3 SPI1 Paths with dashed lines cross the subchip boundary EDMA3_0_CC0 EDMA3_0_CC0 SPRUGX5A – May 2011 System Interconnect Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 35: System Memory
SPRUGX5A – May 2011 System Memory ........................... Topic Page ...................... Introduction ....................ARM Memories ..................On-Chip RAM Memory ..................... External Memories ................... Internal Peripherals ....................... Peripherals SPRUGX5A – May 2011 System Memory Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 36: Introduction
(PLLC), the power and sleep controller (PSC), and the system configuration module (SYSCFG). See the device-specific data manual for the complete list of peripherals supported on your device. SPRUGX5A – May 2011 System Memory Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 37: Memory Protection Unit (Mpu)
Chapter 5 SPRUGX5A – May 2011 Memory Protection Unit (MPU) ........................... Topic Page ...................... Introduction ...................... Architecture ....................MPU Registers SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 38: Introduction
(MPU_ADDR_ERR_INT) and a protection interrupt (MPU_PROT_ERR_INT). Figure 5-1. MPU Block Diagram Input Output Protection Data Data Checks MPU_ADDR_ERR_INT MMRs MPU_PROT_ERR_INT MPU Register Bus SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 39: Mpu Default Configuration
In some cases, a particular setting depends on software being executed at the time of the access or the configuration of the master peripheral. SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 40: Memory Protection Ranges
Figure 5-2. Permission Fields Reserved Allowed IDs AID11 AID10 AID9 AID8 AID7 AID6 Allowed IDs Reserved Access Types AID5 AID4 AID3 AID2 AID1 AID0 SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 41: Request Type Access Controls
Table 5-4. Request Type Access Controls Field Description Supervisor may read Supervisor may write Supervisor may execute User may read User may write User may execute SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 42: Protection Check
5.2.7 Reset Considerations After reset, the memory protection page attribute registers (MPPA) default to 0. This disables all protection features. SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 43: Interrupt Support
BOOTCFG_ADDR_ERR Boot configuration address error BOOTCFG_PROT_ERR Boot configuration protection error 5.2.9 Emulation Considerations Memory and MPU registers are not protected against emulation accesses. SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 44: Mpu Registers
01E1 5108h FXD_MPPA Fixed range memory protection page attributes register Section 5.3.9 01E1 5200h PROG1_MPSAR Programmable range 1 start address register Section 5.3.10.2 Memory Protection Unit (MPU) SPRUGX5A – May 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 45 01E1 5300h FLTADDRR Fault address register Section 5.3.13 01E1 5304h FLTSTAT Fault status register Section 5.3.14 01E1 5308h FLTCLR Fault clear register Section 5.3.15 SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 46: Revision Identification Register (Revid)
Assume allowed. When an address is not covered by any MPU protection range, this bit determines whether the transfer is assumed to be allowed or not allowed. Assume is disallowed. Assume is allowed. SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 47: Interrupt Raw Status/Set Register (Irawstat)
Protection violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the status; writing 0 has no effect. Interrupt is not set. Interrupt is set. SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 48: Interrupt Enable Status/Clear Register (Ienstat)
If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0 has no effect. Interrupt is not set. Interrupt is set. SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 49: Interrupt Enable Set Register (Ienset)
Address violation error disable. Writing 0 has no effect. Interrupt is cleared/disabled. PROTERR_CLR Protection violation error disable. Writing 0 has no effect. Interrupt is cleared/disabled. SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 50: Fixed Range Start Address Register (Fxd_Mpsar)
(FXD_MPSAR), which instead read as 0. The FXD_MPEAR is shown in Figure 5-10. Figure 5-10. Fixed Range End Address Register (FXD_MPEAR) Reserved LEGEND: R = Read only; -n = value after reset SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 51: Fixed Range Memory Protection Page Attributes Register (Fxd_Mppa)
Access is denied. Access is allowed. User Write permission. Access is denied. Access is allowed. User Execute permission. Access is denied. Access is allowed. SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 52: Programmable Range N Start Address Registers (Progn_Mpsar)
Table 5-16. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions Field Value Description 31-16 START_ADDR C000h–DFFFh Start address for range N. 15-0 Reserved Reserved SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 53: Programmable Range N End Address Registers (Progn_Mpear)
Table 5-18. MPU2 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions Field Value Description 31-16 END_ADDR C000h–DFFFh Start address for range N. 15-0 Reserved FFFFh Reserved SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 54: Programmable Range N Memory Protection Page Attributes Register (Progn_Mppa)
Access is denied. Access is allowed. User Write permission. Access is denied. Access is allowed. User Execute permission. Access is denied. Access is allowed. SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 55: Fault Address Register (Fltaddrr)
LEGEND: R = Read only; -n = value after reset Table 5-20. Fault Address Register (FLTADDRR) Field Descriptions Field Value Description 31-0 FLTADDR 0-FFFF FFFFh Memory address of fault. SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 56: Fault Status Register (Fltstat)
9h-Fh Reserved Supervisor write fault. Reserved Relaxed cache write back fault. 13h-1Fh Reserved Supervisor read fault. 21h-3Eh Reserved Relaxed cache line fill fault. SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 57: Fault Clear Register (Fltclr)
Value Description 31-1 Reserved Reserved CLEAR Command to clear the current fault. Writing 0 has no effect. No effect. Clear the current fault. SPRUGX5A – May 2011 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 59: Device Clocking
Chapter 6 SPRUGX5A – May 2011 Device Clocking ........................... Topic Page ......................Overview ..................Frequency Flexibility ................... Peripheral Clocking SPRUGX5A – May 2011 Device Clocking Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 60: Overview
Not Applicable Not Applicable PLL0 input reference clock PLL1_SYSCLK3 Not Applicable Not Applicable (not configured by default) UART1/2, Timer64P2/3, McASP0, SPI1 ASYNC3 Not Applicable Not Applicable SPRUGX5A – May 2011 Device Clocking Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 61: Overall Clocking Diagram
Section 6.3.1 for USB clocking. Section 6.3.2 for DDR2/mDDR clocking. Section 6.3.3 for EMIFA clocking. Section 6.3.4 for EMAC clocking. Section 6.3.5 for McASP clocking. SPRUGX5A – May 2011 Device Clocking Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 62: Frequency Flexibility
PLLM setting of ×24 and a POSTDIV setting of /3, even though both of these modes would result in a CPU frequency of 200 MHz. Device Clocking SPRUGX5A – May 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 63: Peripheral Clocking
PLL0_AUXCLK must be 12, 24, 48, 19.2, 38.4, 13, 26, 20, or 40 MHz. The PLL inside the USB2.0 PHY can be configured to accept any of these input clock frequencies. SPRUGX5A – May 2011 Device Clocking Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 64: Ddr2/Mddr Memory Controller Clocking
DDR2/mDDR memory controller via the LPSC while still providing a clock on the DDR_CLK and DDR_CLK. NOTE: DDR_CLK and DDR_CLK are output clock signals. SPRUGX5A – May 2011 Device Clocking Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 65: Ddr2/Mddr Memory Controller Clocking Diagram
264 MHz 8000h 264 MHz 132 MHz 504 MHz Div2 252 MHz 8000h 252 MHz 126 MHz Section 6.2 for explanation of POSTDIV divider modes. SPRUGX5A – May 2011 Device Clocking Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 66: Emifa Clocking
The maximum frequency supported by EMIFA is 100 MHz. The 133 MHz is outside of the supported frequency range for EMIFA and, therefore, is not supported. Device Clocking SPRUGX5A – May 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 67: Emac Clocking
1000 0000 3-State 0000 1000 RMII_MHZ_50_CLK Signal NOTE: The SYSCLK7 output clock does not meet the RMII reference clock specification of 50 MHz +/-50 ppm. SPRUGX5A – May 2011 Device Clocking Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 68: Mcasp Clocking
Figure 6-6. McASP Clocking Diagram On Chip CFGCHIP3[ASYNC3_CLKSRC] Module PLL0_SYSCLK2 Clock LPSC McASP0 PLL1_SYSCLK2 TX/RX Reference Clock Clock Frame Sync PLL0_AUXCLK Generator Generator ACLKX AHCLKX AFSX AFSR ACLKR AHCLKR SPRUGX5A – May 2011 Device Clocking Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 69: I/O Domains
PLL0_SYSCLK2 or clocks, or externally generated Peripheral Serial Clock asynchronous clocks. SPI1 ASYNC3 or Peripheral Serial Clock EMAC PLL0_SYSCLK4 or RMII_MHZ_50_CLK USB2.0 USB_REFCLKIN or AUXCLK SPRUGX5A – May 2011 Device Clocking Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 71: Phase-Locked Loop Controller (Pllc)
Chapter 7 SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) ........................... Topic Page ...................... Introduction ....................PLL Controllers ....................PLLC Registers SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 72: Introduction
PLL mode operation (set the PLLEN bit in PLLCTL to 1). The PLL controller registers are listed in Section 7.3. SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 73: Pllc Structure
PLL Controller 1 PLLDIV2 (/2) SYSCLK2 PLLDIV3 (/3) SYSCLK3 POSTDIV PLLDIV1 (/1) SYSCLK1 PLLM DDR2/mDDR Internal Clock Source SYSCLK1 OSCDIV PLLC1 OBSCLK SYSCLK2 SYSCLK3 OCSEL[OCSRC] SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 74: Device Clock Generation
The PLL0 input clock source can be configured to use PLL1_SYSCLK3 instead of OSCIN by programming the EXTCLKSRC bit in the PLLC0 PLL control register (PLLCTL). The PLL1 input clock source will also be OSCIN. SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 75: Steps For Programming The Plls
4. Set the PLL_MASTER_LOCK bit in CFGCHIP0 and/or the PLL1_MASTER_LOCK bit in CFGCHIP3, as required. 5. Write an incorrect key value to the KICK0R and KICK1R registers. SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 76 6. Wait for the PLL to lock. See the device-specific data manual for PLL lock time. 7. Set the PLLEN bit in PLLCTL to 1 (removes PLL from bypass mode). SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 77: Pllc Registers
Section 7.3.20 01C1 11F0h EMUCNT0 PLLC0 Emulation Performance Counter 0 Register Section 7.3.36 01C1 11F4h EMUCNT1 PLLC0 Emulation Performance Counter 1 Register Section 7.3.37 SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 78: Pllc0 Revision Identification Register (Revid)
LEGEND: R = Read only; -n = value after reset Table 7-4. PLLC0 Revision Identification Register (REVID) Field Descriptions Field Value Description 31-0 4481 3C00h Peripheral revision ID for PLLC0. SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 79: Pllc1 Revision Identification Register (Revid)
Power on reset. Power On Reset (POR) was not the last reset to occur. Power On Reset (POR) was the last reset to occur. SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 80: Pllc0 Reset Control Register (Rsctrl)
RSCTRL unlock key. Key used to enable writes to RSCTRL. Register is locked when read value is 3h. Register is unlocked when read value is Ch. 5A69h RSCTRL unlock key SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 81: Pllc0 Control Register (Pllctl)
PLL0 power-down. PLL0 is operating. PLL0 is powered-down. PLLEN PLL0 mode enables. PLL0 is in bypass mode. PLL0 mode is enabled, not bypassed. SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 82: Pllc1 Control Register (Pllctl)
PLL1 power-down. PLL1 is operating. PLL1 is powered-down. PLLEN PLL1 mode enables. PLL1 is in bypass mode. PLL1 mode is enabled, not bypassed. SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 83: Pllc0 Obsclk Select Register (Ocsel)
0-1Fh PLLC0 OBSCLK source. Output on CLKOUT pin. 0-13h Reserved OSCIN 15h-16h Reserved PLL0_SYSCLK1 PLL0_SYSCLK2 PLL0_SYSCLK3 PLL0_SYSCLK4 PLL0_SYSCLK5 PLL0_SYSCLK6 PLL0_SYSCLK7 PLLC1 OBSCLK Disabled SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 84: Pllc1 Obsclk Select Register (Ocsel)
Table 7-11. PLLC1 OBSCLK Select Register (OCSEL) Field Descriptions Field Value Description 31-5 Reserved Reserved OCSRC 0-1Fh PLLC1 OBSCLK source. 0-13h Reserved OSCIN 15h-16h Reserved PLL1_SYSCLK1 PLL1_SYSCLK2 PLL1_SYSCLK3 1A-1Fh Reserved SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 85: Pll Multiplier Control Register (Pllm)
PLLC0 pre-divider is enabled. 14-5 Reserved Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL pre-divide by 1). SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 86: Pllc0 Divider 1 Register (Plldiv1)
Divider 1 is enabled. 14-5 Reserved Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1). SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 87: Pllc0 Divider 2 Register (Plldiv2)
Divider 2 is enabled. 14-5 Reserved Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL divide by 2). SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 88: Pllc0 Divider 3 Register (Plldiv3)
Divider 3 is enabled. 14-5 Reserved Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 2h (PLL divide by 3). SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 89: Pllc0 Divider 4 Register (Plldiv4)
Divider 5 is enabled. 14-5 Reserved Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults 2 (PLL divide by 3). SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 90: Pllc0 Divider 6 Register (Plldiv6)
Divider 7 is enabled. 14-5 Reserved Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 5 (PLL divide by 6). SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 91: Pllc0 Oscillator Divider 1 Register (Oscdiv)
PLLC1 clock enable control register (CKEN) must be set to 1. 14-5 Reserved Reserved RATIO 0-1Fh Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1. SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 92: Pll Post-Divider Control Register (Postdiv)
Table 7-27. PLL Controller Command Register (PLLCMD) Field Descriptions Field Value Description 31-1 Reserved Reserved GOSET GO bit for phase alignment. Clear bit (no effect) Phase alignment SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 93: Pll Controller Status Register (Pllstat)
Status of GO operation. If 1, indicates GO operation is in progress. GO operation is not in progress. GO operation is in progress. SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 94: Pllc0 Clock Align Control Register (Alnctl)
PLL0_SYSCLK2 needs to be aligned to others selected in this register. ALN1 PLL0_SYSCLK1 needs to be aligned to others selected in this register. SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 95: Pllc1 Clock Align Control Register (Alnctl)
PLL1_SYSCLK2 needs to be aligned to others selected in this register. ALN1 PLL1_SYSCLK1 needs to be aligned to others selected in this register. SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 96: Pllc0 Plldiv Ratio Change Status Register (Dchange)
PLL0_SYSCLK2 divide ratio is modified. Ratio is not modified. Ratio is modified. SYS1 PLL0_SYSCLK1 divide ratio is modified. Ratio is not modified. Ratio is modified. SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 97: Pllc1 Plldiv Ratio Change Status Register (Dchange)
PLL1_SYSCLK2 divide ratio is modified. Ratio is not modified. Ratio is modified. SYS1 PLL1_SYSCLK1 divide ratio is modified. Ratio is not modified. Ratio is modified. SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 98: Pllc0 Clock Enable Control Register (Cken)
PLLC1 OBSCLK is enabled. For PLLC1 OBSCLK to toggle, both the OBSEN bit and the OD1EN bit in the PLLC1 oscillator divider 1 register (OSCDIV) must be set to 1. Reserved Reserved SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 99: Pllc0 Clock Status Register (Ckstat)
AUXCLK on status. PLLC0 AUXCLK is controlled by the AUXEN bit in the PLLC0 clock enable control register (CKEN). PLLC0 AUXCLK is off. PLLC0 AUXCLK is on. SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 100: Pllc1 Clock Status Register (Ckstat)
OBSCLK on status. PLLC1 OBSCLK is controlled in the PLLC1 oscillator divider 1 register (OSCDIV) by the OBSEN bit in the PLLC1 clock enable control register (CKEN). PLLC1 OBSCLK is off. PLLC1 OBSCLK is on. Reserved Reserved SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 101: Pllc0 Sysclk Status Register (Systat)
PLL0_SYSCLK6 on status. SYS5ON PLL0_SYSCLK5 on status. SYS4ON PLL0_SYSCLK4 on status. SYS3ON PLL0_SYSCLK3 on status. SYS2ON PLL0_SYSCLK2 on status. SYS1ON PLL0_SYSCLK1 on status. SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 102: Pllc1 Sysclk Status Register (Systat)
Table 7-38. PLLC1 SYSCLK Status Register (SYSTAT) Field Descriptions Field Value Description 31-3 Reserved Reserved SYS3ON PLL1_SYSCLK3 on status. SYS2ON PLL1_SYSCLK2 on status. SYS1ON PLL1_SYSCLK1 on status. SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 103: Emulation Performance Counter 0 Register (Emucnt0)
LEGEND: R = Read only; -n = value after reset Table 7-40. Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions Field Value Description 31-0 COUNT 0-FFFF FFFFh Counter value for upper 64-bits. SPRUGX5A – May 2011 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 105: Power And Sleep Controller (Psc)
Power Domain and Module Topology ................Executing State Transitions ..............IcePick Emulation Support in the PSC ....................PSC Interrupts ....................PSC Registers SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 106: Introduction
EDMA3_0 Transfer Controller 1 AlwaysON (PD0) SwRstDisable — EMIFA (BR7) AlwaysON (PD0) SwRstDisable — — SPI0 AlwaysON (PD0) SwRstDisable MMC/SD0 AlwaysON (PD0) SwRstDisable — 106 Power and Sleep Controller (PSC) SPRUGX5A – May 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 107: Psc1 Default Module Configuration
AlwaysON (PD0) Enable SCR F7 AlwaysON (PD0) Enable SCR F8 AlwaysON (PD0) Enable Not Used — — — — On-chip RAM PD_SHRAM Enable SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 108: Power Domain States
Disable, SyncReset, or SwRstDisable state the power sleep controller ignores these transition requests and transitions the module state to Enable. SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 109 It is not envisioned to use this mode when peripherals are fully operational and moving data. See Section 8.2.2.1 for additional considerations, constraints, limitations around this mode. SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 110: Executing State Transitions
4. Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. The modules are safely in the new states only after the GOSTAT[x] bit in PTSTAT is cleared to 0. SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 111: Icepick Emulation Support In The Psc
NEXT bit in the MDCTL/PDCTL registers. IcePick support only applies to the modules listed in Section 8.4; therefore, the PSC interrupt conditions only apply to those modules listed. SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 112: Interrupt Registers
Set the ALLEV bit in the INTEVAL before exiting your PSC interrupt service routine to ensure that you do not miss any PSC interrupts. Section 8.6 for a description of the PSC registers. SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 113: Interrupt Handling
(d) Set the ALLEV bit in INTEVAL. Setting this bit reasserts the PSC interrupt to the device interrupt controller, if there are still any active interrupt events. SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 114: Psc Registers
Module Status n Register (modules 0-31) Section 8.6.17 01E2 787Ch MDSTAT31 01E2 7A00h- MDCTL0- Module Control n Register (modules 0-31) Section 8.6.19 01E2 7A7Ch MDCTL31 114 Power and Sleep Controller (PSC) SPRUGX5A – May 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 115: Revision Identification Register (Revid)
Reserved Reserved ALLEV Evaluate PSC interrupt (PSCn_ALLINT). A write of 0 has no effect. A write of 1 re-evaluates the interrupt condition. SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 116: Psc0 Module Error Pending Register 0 (Modules 0-15) (Merrpr0)
Figure 8-4. Figure 8-4. PSC1 Module Error Pending Register 0 (MERRPR0) Reserved LEGEND: R = Read only; -n = value after reset SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 117: Psc0 Module Error Clear Register 0 (Modules 0-15) (Merrcr0)
Figure 8-6. Figure 8-6. PSC1 Module Error Clear Register 0 (MERRCR0) Reserved LEGEND: R = Read only; -n = value after reset SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 118: Power Error Pending Register (Perrpr)
A write of 0 has no effect. A write of 1 clears the P bit in PERRPR and the interrupt status bits in PDSTAT1. Reserved Reserved SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 119: Power Domain Transition Command Register (Ptcmd)
MDCTL.NEXT for all the modules residing on this domain). If any of the NEXT fields are not matching the corresponding current state (MDSTAT.STATE), the PSC will transition those respective domain/modules to the new NEXT state. SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 120: Power Domain Transition Status Register (Ptstat)
Always ON (PD0) power domain transition status. No transition in progress. Modules in Always ON power domain are transitioning. Always On power domain is transitioning. SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 121: Power Domain 0 Status Register (Pdstat0)
Power domain is in the off state. Power domain is in the on state. 2h-Fh Reserved 10h-1Ah Power domain is in transition. 1Bh-1Fh Reserved SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 122: Power Domain 1 Status Register (Pdstat1)
Power domain is in the off state. Power domain is in the on state. 2h-Fh Reserved 10h-1Ah Power domain is in transition. 1Bh-1Fh Reserved SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 123: Power Domain 0 Control Register (Pdctl0)
Power domain next state. For Always ON power domain this bit is read/write, but writes have no effect since internally this power domain always remains in the on state. Power domain off. Power domain on. SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 124: Power Domain 1 Control Register (Pdctl1)
Emulation alters power domain state interrupt enable. Disable interrupt. Enable interrupt. Reserved Reserved Reserved Reserved NEXT User-desired power domain next state. Power domain off. Power domain on. SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 125: Power Domain 0 Configuration Register (Pdcfg0)
Not a RAM power domain. RAM power domain. ALWAYSON Always ON power domain. Not an Always ON power domain. Always ON power domain. SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 126: Power Domain 1 Configuration Register (Pdcfg1)
Not a RAM power domain. RAM power domain. ALWAYSON Always ON power domain. Not an Always ON power domain. Always ON power domain. SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 127: Module Status N Register (Mdstatn)
Reserved Reserved STATE 0-3Fh Module state status: indicates current module status. SwRstDisable state SyncReset state Disable state Enable state 4h-3Fh Indicates transition SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 128: Psc0 Module Control N Register (Modules 0-15) (Mdctln)
Module local reset control. This bit applies to ARM module (module 14). Assert local reset De-assert local reset Reserved Reserved NEXT 0-3h Module next state. SwRstDisable state SyncReset state Disable state Enable state SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 129: Psc1 Module Control N Register (Modules 0-31) (Mdctln)
Force is disabled. Force is enabled. 30-3 Reserved Reserved NEXT 0-3h Module next state. SwRstDisable state SyncReset state Disable state Enable state SPRUGX5A – May 2011 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 131: Power Management
ARM Sleep Mode Management ....................RTC-Only Mode ..........Dynamic Voltage and Frequency Scaling (DVFS) ..................... Deep Sleep Mode ........9.10 Additional Peripheral Power Management Considerations SPRUGX5A – May 2011 Power Management Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 132: Introduction
Together these modules play a significant role in managing the clocks from a power management feature standpoint. For detailed information on the PSC, see Chapter 8. For detailed information on the PLLC0 and PLLC1, see Chapter 6 Chapter SPRUGX5A – May 2011 Power Management Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 133: Features
Minimizes the I/O power consumption. receiver disable Internal pull-up and The internal pull-ups and pull-downs are Reduces the I/O leakage power. pull-down resistor enabled/disabled by groups. control SPRUGX5A – May 2011 Power Management Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 134: Clock Management
PLL lock time when switching back to a normal operating level. Chapter 6 Chapter 7 describe PLL bypass and PLL power down. SPRUGX5A – May 2011 Power Management Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 135: Arm Sleep Mode Management
GPIO or watchdog timer) must not be disabled, or the device will never wake up. For more information on this sleep mode, see the ARM926EJ-S Technical Reference Manual (TRM), downloadable from http://infocenter.arm.com/help/index.jsp. SPRUGX5A – May 2011 Power Management Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 136: Arm Clock Off
ARM (to exit the wait-for-interrupt mode). This example assumes that the ARM enabled this interrupt before entering its wait-for-interrupt sleep mode state. SPRUGX5A – May 2011 Power Management Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 137: Rtc-Only Mode
When applying DVFS, a processor or system always runs at the lowest OPP that meets the performance requirement at a given time. You determine the optimal OPP for a given task and then switch to that OPP to save power. SPRUGX5A – May 2011 Power Management Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 138: Frequency Scaling Considerations
Care must be taken such that the maximum operating frequency supported at the new voltage is not violated. For this reason, it is recommended to change the operating frequency before switching the operating voltage. SPRUGX5A – May 2011 Power Management Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 139: Deep Sleep Mode
5. Enable the clocks to the DDR2/mDDR memory controller, reset the DDR PHY, and then take the DDR2/mDDR out of self-refresh mode. 6. Configure the desired states to the peripherals and enable as required. SPRUGX5A – May 2011 Power Management Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 140: Entering/Exiting Deep Sleep Mode Using Rtc Controlled Wake-Up
6. Configure the desired states to the peripherals and enable as required. For more details on the clock enable procedure of the DDR2/mDDR memory controller, see the AM17x/AM18x ARM Microprocessor DDR2/mDDR Memory Controller User's Guide (SPRUFU3). SPRUGX5A – May 2011 Power Management Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 141: Deep Sleep Sequence
8. Software clears the SLEEPENABLE bit. The SLEEPCOMPLETE bit is automatically cleared. Figure 9-1. Deep Sleep Mode Sequence See Note: SLEEPENABLE (internal) DEEPSLEEP CLKGATE (internal) PLLC Ref Clk (internal) OSC_GZ (internal) OSCIN SLEEPCOMPLETE (internal) SPRUGX5A – May 2011 Power Management Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 142: Entering/Exiting Deep Sleep Mode Using Software Handshaking
PHY logic. You can put the USB2.0 PHY and OTG module in the lowest power state, when not in use, by writing to the USB0PHYPWDN and the USB0OTGPWRDN bits in the chip configuration 2 register (CFGCHIP2) of the system configuration (SYSCFG) module. SPRUGX5A – May 2011 Power Management Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 143: Ddr2/Mddr Memory Controller Clock Gating And Self-Refresh Mode
Internal resistors are disabled through the pullup/pulldown enable register (PUPD_ENA) in the system configuration module (Chapter 10). SPRUGX5A – May 2011 Power Management Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 145: System Configuration (Syscfg) Module
SPRUGX5A – May 2011 System Configuration (SYSCFG) Module ........................... Topic Page ....................10.1 Introduction ....................... 10.2 Protection ..................10.3 Master Priority Control ................... 10.4 SYSCFG Registers SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 146: Introduction
Supervisor mode. The registers that can only be accessed in privileged mode are listed in Section 10.4. See the ARM926EJ-S Technical Reference Manual (TRM), downloadable from http://infocenter.arm.com/help/index.jsp for details on privilege levels. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 147: Kicker Mechanism Protection
EDMA3_0_TC1 - read EDMA3_0_TC1 - write EDMA3_1_TC0 – read EDMA3_1_TC0 – write 22-33 Reserved USB2.0 CFG USB2.0 DMA 36-37 Reserved EMAC 39-255 Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 148: Syscfg Registers
Privileged mode Section 10.4.9.1 01C1 4124h PINMUX1 Pin Multiplexing Control 1 Register Privileged mode Section 10.4.9.2 This register is for internal-use only. 148 System Configuration (SYSCFG) Module SPRUGX5A – May 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 149: System Configuration Module 1 (Syscfg1) Registers
Privileged mode Section 10.4.21 01E2 C010h PUPD_SEL Pullup/Pulldown Selection Register Privileged mode Section 10.4.22 01E2 C014h RXACTIVE RXACTIVE Control Register Privileged mode Section 10.4.23 SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 150: Revision Identification Register (Revid)
Device identification. For silicon revision 1.0, n = 0. For silicon revision 1.1, n = 0. For silicon revision 2.0, n = 1. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 151: Boot Configuration Register (Bootcfg)
Table 10-7. Boot Configuration Register (BOOTCFG) Field Descriptions Field Value Description 31-16 Reserved Reserved 15-0 BOOTMODE 0-FFFFh Boot Mode. This reflects the state of the boot mode pins. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 152: Kick Registers (Kick0R-Kick1R)
MMRs. The written data must be 95A4 F1E0h to unlock this register. KICK0R must be written before writing to the kick1 register. Writing any other value will lock the other MMRs. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 153: Host 0 Configuration Register (Host0Cfg)
Reserved Reserved BOOTRDY ARM boot ready bit allowing ARM to boot. ARM held in reset mode. ARM released from wait in reset mode. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 154: Interrupt Registers
Protection violation error. Reading this bit field reflects the raw status of the interrupt before enabling. Indicates the interrupt is not set. Writing 0 has no effect. Indicates the interrupt is set. Writing 1 sets the status. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 155: Interrupt Enable Status/Clear Register (Ienstat)
Protection violation error. Reading this bit field reflects the interrupt enabled status. Indicates the interrupt is not set. Writing 0 has no effect. Indicates the interrupt is set. Writing 1 clears the status. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 156: Interrupt Enable Register (Ienset)
Writing a 0 has not effect. Writing a 1 clears/disables this interrupt. PROTERR_CLR Protection violation error. Writing a 0 has not effect. Writing a 1 clears/disables this interrupt. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 157: Fault Registers
LEGEND: R = Read only; -n = value after reset Table 10-16. Fault Address Register (FLTADDRR) Field Descriptions Field Value Description 31-0 FLTADDR 0-FFFF FFFFh Fault address for the first fault transfer. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 158: Fault Status Register (Fltstat)
User write fault Reserved User read fault 5h-7h Reserved Supervisor execute fault 9h-Fh Reserved Supervisor write fault 11h-1Fh Reserved Supervisor read fault 21h-3Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 159: Master Priority Registers (Mstpri0-Mstpri2)
Reserved. Always read as 0. ARM_I 0-7h ARM_I port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest). SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 160: Master Priority 1 Register (Mstpri1)
Reserved. Write the default value to all bits when modifying this register. Reserved Reserved. Always read as 0. Reserved Reserved. Write the default value to all bits when modifying this register. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 161: Master Priority 2 Register (Mstpri2)
Reserved. Write the default value when modifying this register. EMAC 0-7h EMAC port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest). SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 162: Pin Multiplexing Control Registers (Pinmux0-Pinmux19)
5h-7h Reserved Selects Function GP0[9] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 163 2h-7h Reserved Selects Function GP0[14] 9h-Fh Reserved PINMUX0_3_0 ACLKR/GP0[15] Control Pin is 3-stated. Selects Function ACLKR 2h-7h Reserved Selects Function GP0[15] 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 164: Pin Multiplexing Control 1 Register (Pinmux1)
2h-7h Reserved Selects Function GP0[4] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 165 2h-7h Reserved Selects Function GP0[6] 9h-Fh Reserved PINMUX1_3_0 AXR15/GP0[7] Control Pin is 3-stated. Selects Function AXR15 2h-7h Reserved Selects Function GP0[7] 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 166: Pin Multiplexing Control 2 Register (Pinmux2)
5h-7h Reserved Selects Function MII_TXD[3] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 167 5h-7h Reserved Selects Function MII_TXEN 9h-Fh Reserved PINMUX2_3_0 AXR7/GP1[15] Control Pin is 3-stated. Selects Function AXR7 2h-7h Reserved Selects Function GP1[15] 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 168: Pin Multiplexing Control 3 Register (Pinmux3)
5h-7h Reserved Selects Function MII_RXD[2] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 169 9h-Fh Reserved PINMUX3_3_0 SPI0_CLK/GP1[8]/MII_RXCLK Control Pin is 3-stated. Selects Function SPI0_CLK 2h-3h Reserved Selects Function GP1[8] 5h-7h Reserved Selects Function MII_RXCLK 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 170: Pin Multiplexing Control 4 Register (Pinmux4)
3h-7h Reserved Selects Function GP1[3] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 171 PINMUX4_3_0 SPI0_SCS[1]/TM64P0_OUT12/GP1[7]/MDIO_CLK/TM64P0_IN12 Control Selects Function TM64P0_IN12 Selects Function SPI0_SCS[1] Selects Function TM64P0_OUT12 Reserved Selects Function GP1[7] 5h-7h Reserved Selects Function MDIO_CLK 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 172: Pin Multiplexing Control 5 Register (Pinmux5)
2h-7h Reserved Selects Function GP2[12] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 173 2h-7h Reserved Selects Function GP2[14] 9h-Fh Reserved PINMUX5_3_0 SPI1_SCS[1]/GP2[15]/TM64P2_IN12 Control Selects Function TM64P2_IN12 Selects Function SPI1_SCS[1] 2h-7h Reserved Selects Function GP2[15] 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 174: Pin Multiplexing Control 6 Register (Pinmux6)
2h-7h Reserved Selects Function GP2[4] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 175 2h-7h Reserved Selects Function GP2[6] 9h-Fh Reserved PINMUX6_3_0 EMA_CLK/GP2[7] Control Pin is 3-stated. Selects Function EMA_CLK 2h-7h Reserved Selects Function GP2[7] 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 176: Pin Multiplexing Control 7 Register (Pinmux7)
2h-7h Reserved Selects Function GP3[12] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 177 2h-7h Reserved Selects Function GP3[14] 9h-Fh Reserved PINMUX7_3_0 EMA_CS[2]/GP3[15] Control Pin is 3-stated. Selects Function EMA_CS[2] 2h-7h Reserved Selects Function GP3[15] 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 178: Pin Multiplexing Control 8 Register (Pinmux8)
2h-7h Reserved Selects Function GP3[4] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 179 2h-7h Reserved Selects Function GP3[6] 9h-Fh Reserved PINMUX8_3_0 EMA_D[15]/GP3[7] Control Pin is 3-stated. Selects Function EMA_D[15] 2h-7h Reserved Selects Function GP3[7] 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 180: Pin Multiplexing Control 9 Register (Pinmux9)
2h-7h Reserved Selects Function GP4[12] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 181 2h-7h Reserved Selects Function GP4[14] 9h-Fh Reserved PINMUX9_3_0 EMA_D[7]/GP4[15] Control Pin is 3-stated. Selects Function EMA_D[7] 2h-7h Reserved Selects Function GP4[15] 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 182: Pin Multiplexing Control 10 Register (Pinmux10)
3h-7h Reserved Selects Function GP4[4] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 183 Reserved Selects Function GP4[6] 9h-Fh Reserved PINMUX10_3_0 MMCSD0_CLK/GP4[7] Control Pin is 3-stated. Reserved Selects Function MMCSD0_CLK 3h-7h Reserved Selects Function GP4[7] 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 184: Pin Multiplexing Control 11 Register (Pinmux11)
2h-7h Reserved Selects Function GP5[12] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 185 Selects Function GP5[14] 9h-Fh Reserved PINMUX11_3_0 EMA_A[15]/MMCSD0_DAT[6]/GP5[15] Control Pin is 3-stated. Selects Function EMA_A[15] Selects Function MMCSD0_DAT[6] 3h-7h Reserved Selects Function GP5[15] 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 186: Pin Multiplexing Control 12 Register (Pinmux12)
2h-7h Reserved Selects Function GP5[4] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 187 2h-7h Reserved Selects Function GP5[6] 9h-Fh Reserved PINMUX12_3_0 EMA_A[7]/GP5[7] Control Pin is 3-stated. Selects Function EMA_A[7] 2h-7h Reserved Selects Function GP5[7] 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 188: Pin Multiplexing Control 13 Register (Pinmux13)
1h-7h Reserved Selects Function GP6[13] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 189 2h-7h Reserved Selects Function GP6[14] 9h-Fh Reserved PINMUX13_3_0 RESETOUT/GP6[15] Control Selects Function RESETOUT Selects Function RESETOUT 2h-7h Reserved Selects Function GP6[15] 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 190: Pin Multiplexing Control 14 Register (Pinmux14)
1h-7h Reserved Selects Function GP6[6] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 191 Table 10-35. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions (continued) Field Value Description Type PINMUX14_3_0 GP6[7] Control Pin is 3-stated. 1h-7h Reserved Selects Function GP6[7] 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 192: Pin Multiplexing Control 15 Register (Pinmux15)
Section 6.3.4 for more information. 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 193: Pin Multiplexing Control 16 Register (Pinmux16)
3h-7h Reserved Selects Function GP6[5] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 194 Table 10-37. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions (continued) Field Value Description Type PINMUX16_3_0 PINMUX16_3_0 Control Pin is 3-stated. 1h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 195: Pin Multiplexing Control 17 Register (Pinmux17)
1h-7h Reserved Selects Function GP7[8] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 196 Table 10-38. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions (continued) Field Value Description Type PINMUX17_3_0 GP7[9] Control Pin is 3-stated. 1h-7h Reserved Selects Function GP7[9] 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 197: Pin Multiplexing Control 18 Register (Pinmux18)
1h-7h Reserved Selects Function GP7[0] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 198 Table 10-39. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions (continued) Field Value Description Type PINMUX18_3_0 GP7[1]/BOOT[1] Control Selects Function BOOT[1] 1h-7h Reserved Selects Function GP7[1] 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 199: Pin Multiplexing Control 19 Register (Pinmux19)
1h-7h Reserved Selects Function GP6[4] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 200 Pin is 3-stated. 1h-7h Reserved Selects Function GP8[8] 9h-Fh Reserved PINMUX19_3_0 GP8[9] Control Pin is 3-stated. 1h-7h Reserved Selects Function GP8[9] 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 201: Suspend Source Register (Suspsrc)
ARM is the source of the emulation suspend. No emulation suspend. UART1SRC UART1 Emulation Suspend Source. ARM is the source of the emulation suspend. No emulation suspend. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 202 ARM is the source of the emulation suspend. No emulation suspend. Reserved Reserved. Write the default value to all bits when modifying this register. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 203: Chip Signal Register (Chipsig)
Asserts SYSCFG_CHIPINT2 interrupt. No effect Asserts interrupt CHIPSIG1 Asserts SYSCFG_CHIPINT1 interrupt. No effect Asserts interrupt CHIPSIG0 Asserts SYSCFG_CHIPINT0 interrupt. No effect Asserts interrupt SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 204: Chip Signal Clear Register (Chipsig_Clr)
Clears SYSCFG_CHIPINT2 interrupt. No effect Clears interrupt CHIPSIG1 Clears SYSCFG_CHIPINT1 interrupt. No effect Clears interrupt CHIPSIG0 Clears SYSCFG_CHIPINT0 interrupt. No effect Clears interrupt SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 205: Chip Configuration 0 Register (Cfgchip0)
EDMA3_0_TC1 Default Burst Size (DBS). 16 bytes 32 bytes 64 bytes Reserved EDMA30TC0DBS EDMA3_0_TC0 Default Burst Size (DBS). 16 bytes 32 bytes 64 bytes Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 206: Chip Configuration 1 Register (Cfgchip1)
GPIO Interrupt from Bank 3 GPIO Interrupt from Bank 4 GPIO Interrupt from Bank 5 GPIO Interrupt from Bank 6 GPIO Interrupt from Bank 7 9h-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 207: Chip Configuration 2 Register (Cfgchip2)
USB2.0 OTG subsystem (SS) operation state control. OTG SS is enabled and is in operating state (normal operation). OTG SS is disabled and is powered down. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 208 USB2.0 PHY reference clock input frequencies. Reserved 12 MHz 24 MHz 48 MHz 19.2 MHz 38.4 MHz 13 MHz 26 MHz 20 MHz 40 MHz Ah-Fh Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 209: Chip Configuration 3 Register (Cfgchip3)
Clock source for EMIFA clock domain. Clock driven by PLL0_SYSCLK3 Clock driven by DIV4.5 PLL output Reserved Reserved. Write the default value when modifying this register. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 210: Chip Configuration 4 Register (Cfgchip4)
LOCK POWERDN R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 211: Vtp I/O Control Register (Vtpio_Ctl)
Drive strength control bit. Drive strength control bit. Drive strength control bit. Digital filter control bit. Digital filter control bit. Digital filter control bit. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 212: Ddr Slew Register (Ddr_Slew)
Slew rate mode control status for command macro. Slew rate control is not supported on this device. Slew rate control is off. 1h-3h Reserved SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 213: Deep Sleep Register (Deepsleep)
Deep sleep counter. Number of cycles to count prior to the oscillator being stable. All 16 bits are tied directly to the counter in the Deep Sleep logic. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 214: Pullup/Pulldown Enable Register (Pupd_Ena)
(PUPD_ENA). Internal pull-down functionality for pin group n is enabled. Internal pull-up functionality for pin group n is enabled. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 215: Pullup/Pulldown Select Register (Pupd_Sel) Default Values
Pin Group CP[2] is configured for pull-up by default. PUPDSEL[1] Pin Group CP[1] is configured for pull-up by default. PUPDSEL[0] Pin Group CP[0] is configured for pull-up by default. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 216: Rxactive Control Register (Rxactive)
Receivers should only be disabled if the associated pin group is not being used. LVCMOS receivers for pin group n are disabled. LVCMOS receivers for pin group n are enabled. SPRUGX5A – May 2011 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 217: Arm Interrupt Controller (Aintc)
SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) ........................... Topic Page ....................11.1 Introduction .................... 11.2 Interrupt Mapping ..................11.3 AINTC Methodology ....................11.4 AINTC Registers SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 218: Introduction
Channel 0 Peripheral A Intr 1 Channel 1 Channel 2 Intr (n–1) Peripheral Z Intr n Channel m n ≤ 100 m ≤ 31 SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 219: Aintc System Interrupt Assignments
GPIO Bank 6 Interrupt GPIO_B7INT GPIO Bank 7 Interrupt GPIO_B8INT GPIO Bank 8 Interrupt 51-52 — Reserved UART_INT1 UART1 Interrupt MCASP_INT McASP0 Combined RX/TX Interrupt SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 220 EDMA3_1 Channel Controller 0 Error Interrupt EDMA3_1_TC0_ERRINT EDMA3_1 Transfer Controller 0 Error Interrupt T64P3_ALL Timer64P3 Combined Interrupt (TINT12 and TINT34) 97-100 — Reserved SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 221: Aintc Methodology
Conversion of polarity to active high • Conversion of interrupt type to pulse interrupts After the processing block, all interrupts will be active-high pulses. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 222: Interrupt Enabling
When multiple channels are mapped to the same host interrupt, then prioritization is done to select which interrupt is in the highest-priority channel and which should be sent first to the host. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 223: Interrupt Prioritization
(HINLR1 and HINLR2) display and control the nesting level for each host interrupt. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 224: Interrupt Vectorization
ISR null address. When there is a pending interrupt then the ISR address is calculated as exact base + offset for that interrupt number. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 225: Interrupt Status Clearing
Section 11.4.28 FFFE E384h ECR2 System Interrupt Enable Clear Register 2 Section 11.4.29 FFFE E388h ECR3 System Interrupt Enable Clear Register 3 Section 11.4.30 SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 226: Revision Identification Register (Revid)
LEGEND: R = Read only; -n = value after reset Table 11-3. Revision Identification Register (REVID) Field Descriptions Field Value Description 31-0 4E82 A900h Revision ID of the AINTC. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 227: Control Register (Cr)
NESTMODE 0-3h Nesting mode. No nesting Automatic individual nesting (per host interrupt) Automatic global nesting (over all host interrupts) Manual nesting Reserved Reserved SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 228: Global Enable Register (Ger)
The current global nesting level (highest channel that is nested). Writes set the nesting level. In autonesting mode this value is updated internally, unless the auto_override bit is set. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 229: System Interrupt Status Indexed Set Register (Sisr)
Field Value Description 31-7 Reserved Reserved INDEX 0-7Fh Writes clear the status of the interrupt given in the INDEX value. Reads return 0. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 230: System Interrupt Enable Indexed Set Register (Eisr)
Field Value Description 31-7 Reserved Reserved INDEX 0-7Fh Writes clear the enable of the interrupt given in the INDEX value. Reads return 0. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 231: Host Interrupt Enable Indexed Set Register (Hieisr)
Writes clear the enable of the host interrupt given in the INDEX value. Reads return 0. Writing a 0 clears FIQ. Writing a 1 clears IRQ. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 232: Vector Base Register (Vbr)
Description 31-8 Reserved Reserved SIZE 0-FFh Size of ISR address spaces. 4 bytes 8 bytes 16 bytes 32 bytes 64 bytes 5h-FFh ... SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 233: Vector Null Register (Vnr)
No Interrupt is pending. Can be used by host to test for a negative value to see if no interrupts are pending. 30-10 Reserved Reserved PRI_INDX 0-3FFh The currently highest priority interrupt index pending across all the host interrupts. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 234: Global Prioritized Vector Register (Gpvr)
Writing a 0 has no effect. Write a 1 in bit position [n] to set the status of the system interrupt n. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 235: System Interrupt Status Raw/Set Register 2 (Srsr2)
Writing a 0 has no effect. Write a 1 in bit position [n] to set the status of the system interrupt n + 64. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 236: System Interrupt Status Raw/Set Register 4 (Srsr4)
(before enabling with the Enable Registers). Writing a 0 has no effect. Write a 1 in bit position [n] to clear the status of the system interrupt n. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 237: System Interrupt Status Enabled/Clear Register 2 (Secr2)
Writing a 0 has no effect. Write a 1 in bit position [n] to clear the status of the system interrupt n + 64. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 238: System Interrupt Status Enabled/Clear Register 4 (Secr4)
System interrupt 0 to 31 enable. Read returns the enable value (0 = disabled, 1 = enabled). Writing a 0 has no effect. Write a 1 in bit position [n] to set the enable for system interrupt n. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 239: System Interrupt Enable Set Register 2 (Esr2)
Writing a 0 has no effect. Write a 1 in bit position [n] to set the enable for system interrupt n + 64. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 240: System Interrupt Enable Set Register 4 (Esr4)
System interrupt 0 to 31 disable. Read returns the enable value (0 = disabled, 1 = enabled). Writing a 0 has no effect. Write a 1 in bit position [n] to clear the enable for system interrupt n. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 241: System Interrupt Enable Clear Register 2 (Ecr2)
Writing a 0 has no effect. Write a 1 in bit position [n] to clear the enable for system interrupt n + 64. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 242: System Interrupt Enable Clear Register 4 (Ecr4)
Sets the host interrupt for channel N + 1. CHNL_N 0-FFh Sets the channel for the system interrupt N. (N ranges from 0 to 100). SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 243: Host Interrupt Prioritized Index Register 1 (Hipir1)
Description NONE No Interrupt is pending. 30-10 Reserved Reserved PRI_INDX 0-3FFh Interrupt number of the highest priority pending interrupt for IRQ host interrupt. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 244: Host Interrupt Nesting Level Register 1 (Hinlr1)
IRQ host interrupt. In auto mode the value is updated internally, unless the OVERRIDE is set and then the write data is used. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 245: Host Interrupt Enable Register (Hier)
Value Description 31-2 Reserved Reserved Enable of IRQ IRQ is disabled. IRQ is enabled. Enable of FIQ FIQ is disabled. FIQ is enabled. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 246: Host Interrupt Prioritized Vector Register 1 (Hipvr1)
Table 11-41. Host Interrupt Prioritized Vector Register 2 (HIPVR2) Field Descriptions Field Value Description 31-0 ADDR 0-FFFF FFFFh The currently highest priority interrupt vector address across for the IRQ host interrupt. SPRUGX5A – May 2011 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 247: Boot Considerations
Chapter 12 SPRUGX5A – May 2011 Boot Considerations ........................... Topic Page ....................12.1 Introduction SPRUGX5A – May 2011 Boot Considerations Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 248 See Using the AM18xx Bootloader Application Report (SPRABA5) for more details on the ROM Boot Loader, a list of boot pins used, and the complete list of supported boot modes. SPRUGX5A – May 2011 Boot Considerations Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 249 Changed second paragraph. Section 11.3.6 Changed second sentence of level 2 in first paragraph. Table 11-34 Changed Description of CHNL_N bit. Section 12.1 Changed first bullet. SPRUGX5A – May 2011 Revision History Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
Page 250 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

Texas Instruments AM1802 Reference Manual

Preface

Overview

ARM Subsystem

Chapter 2

Introduction

Operating States/Modes

Processor Status Registers

Exceptions and Exception Vectors

The 16-BIS/32-BIS Concept

16-BIS/32-BIS Advantages

Co-Processor 15 (CP15)

System Interconnect

System Memory

Memory Protection Unit (MPU)

Device Clocking

Phase-Locked Loop Controller (PLLC)

Power and Sleep Controller (PSC)

Chapter 8

Introduction

Power Domain and Module Topology

Executing State Transitions

Icepick Emulation Support in the PSC

PSC Interrupts

Power Management

System Configuration (SYSCFG) Module

Quick Links

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Summary of Contents for Texas Instruments AM1802