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More than one asynchronous interrupt cause or exception can be present at any time.
However, when more than one interrupt causes exist, only the highest priority interrupt is
taken, as shown in the following table.
NUMBER
1
Development Port Nonmaskable Interrupt
2
System Reset
3
Instruction-Related Interrupts
4
Peripheral Breakpoint Request or
Development Port Maskable Interrupt
5
External Interrupt
6
Decrementer Interrupt
6.4 THE REGISTER UNIT
The fixed-point registers bank holds thirty-two 32-bit fixed-point registers and some control
registers. The register unit holds the general register files of the core and performs the
following operations:
• Decodes the operand fields of all sequential instructions
• Drives the operand buses, as requested by the execution unit
• Performs scoreboard checking and signing
• Samples the resulting data from the writeback bus
MOTOROLA
Table 6-6. Interrupt Priority Mapping
INTERRUPT TYPE
MPC823e REFERENCE MANUAL
CAUSE
Signal from the Development Port
NMI_L Assertion
Instruction Processing
Breakpoint Signal from any Peripheral
Signal from the Interrupt Controller
Decrementer Request
The PowerPC Core
6-15
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