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M30245 Group
2.1.2 Protect Operation
The following explains the protect operation. Figure 2.1.2 shows the set-up procedure.
Operation
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Figure 2.1.2. Set-up procedure for protect function
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
(1) Setting "1" in the write-enable bit of system clock control registers 0 and 1 and frequency
synthesizer-related registers causes system clock control register 0 and 1 and frequency
synthesizer-related registers to be in write-enabled state.
(2) The contents of system clock control register 0 and 1 and these of frequency synthesizer-
related registers are changed.
(3) Setting "0" in PRC0 causes system clock control register 0 and 1 and frequency synthesizer-
related registers to be in write-inhibited state.
(4) To change the contents of processor mode register 0 and that of processor mode register 1,
follow the same steps as in dealing with system clock control registers and frequency synthe-
sizer-related registers.
(1) Clearing the protect (set to write-enabled state)
b7
b0
Protect register [Address 000A
0
1
PRCR
Enables writing to system clock control registers 0 and 1 (addresses 0006
0007
1 : Write-enabled
(2) Setting system clock control register i (i = 0, 1)
(3) Setting the protect (set to write-inhibited state)
b7
b0
Protect register [Address 000A
0
0
PRCR
Enables writing to system clock control registers 0 and 1 (addresses 0006
0007
0 : Write-inhibited
page 5 of 354
]
16
)
and frequency synthesizer-related registers (address 03DB
16
]
16
)
and frequency synthesizer-related registers (address 03DB
16
2. Protect
and
16
to 03DF
)
16
16
and
16
to 03DF
)
16
16
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