Operation Of Serial Interface Special Function; Clock Delay) - Renesas M16C Series User Manual

16-bit single-chip microcomputer
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2.5.5 Operation of Serial Interface Special Function (reception in slave mode with

clock delay)

In receiving data in serial interface special function slave mode, choose functions from those listed in
Table 2.5.4. Operations of the circled items are described below. Figure 2.5.17 shows the operation
timing, and Figures 2.5.18 and 2.5.19 show the set-up procedures.
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Operation
Note
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Table 2.5.4. Choosed functions
Item
Item
Internal clock (f
Transfer clock
source
O
External clock (CLKi pin)
Output reception data at
CLK polarity
O
the rising edge of the
transfer clock
Output reception data at
the falling edge of the
transfer clock
Continuous receive
O
Disabled
mode
Enabled
____
(1) An SSi port is input "L" level which outputs from the transmitter side IC port.
(2) Writing dummy data to the UARTi transmit buffer register, setting the receive enable bit to "1",
and the transmit enable bit to "1", makes the data receivable status ready.
(3) In synchronization with the first rising edge of the transfer clock, the input signal to the SRxDi
pin is stored in the highest bit of the UARTi receive register. Then, data is taken in by shifting
right the content of the UARTi reception data in synchronization with the rising edges of the
transfer clock.
(4) When 1-byte data lines up in the UARTi receive register, the content of the UARTi receive
register is transmitted to the UARTi receive buffer register. At this time, the receive complete
flag and the UARTi receive interrupt request bit goes to "1".
(5) The receive complete flag goes to "0" when the lower-order byte of the UARTi buffer register
is read.
• Set CLKi and SRxDi pins' port direction register to "0".
page 106 of 354
Set-up
Item
/ f
/ f
)
1
8
32
SSi port function
enable
Clock phase set
Serial input port set
2. Serial Interface Special Function
Set-up
SSi function disabled
O
SSi function enabled
Without clock delay
With clock delay
O
T
Di, R
Di selected
X
X
(master mode)
ST
Di, SR
Di selected
X
X
O
(slave mode)

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