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2.5.4 Operation of Serial Interface Special Function (transmission in slave mode
without delay)
In transmitting data in serial interface special function slave mode, choose functions from those listed in
Table 2.5.3. Operations of the circled items are described below. Figure 2.5.14 shows the operation
timing, and Figures 2.5.15 and 2.5.16 show the set-up procedures.
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Operation
Note
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Table 2.5.3. Choosed functions
Item
Item
Internal clock (f
Transfer clock
source
O
External clock (CLKi pin)
Output transmission data at
CLK polarity
O
the falling edge of the
transfer clock
Output transmission data at
the rising edge of the
transfer clock
O
Transmission buffer empty
Transmission
interrupt factor
Transmission complete
____
(1) Input "L" level to an SSi port by the output from the receiver side IC's port.
(2) Setting the transmit enable bit to "1" and writing transmission data to the UARTi transmit
buffer register makes data transmissible status ready.
(3) In synchronization with the first falling edge of the transfer clock, transmission data held in the
UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the
UARTi transmit interrupt request bit goes to "1". Also, the first bit of the transmission data is
transmitted from the STxDi pin. Then the data is transmitted bit by bit from the lower order in
synchronization with the falling edges.
(4) When transmission of 1-byte data is completed, the transmit register empty flag goes to "1",
which indicates that transmission is completed.
(5) If the next transmission data is set in the UARTi transmit buffer register while transmission is
in progress (before the eighth bit has been transmitted), the data is transmitted in succession.
• Set CLKi pin's port direction register to "0".
page 102 of 354
Set-up
Item
/ f
/ f
)
SSi port function
1
8
32
enable
Clock phase set
Serial input port set
2. Serial Interface Special Function
Set-up
SSi function disabled
O
SSi function enabled
Without clock delay
O
With clock delay
T
Di, R
Di selected
X
X
(master mode)
ST
Di, SR
Di selected
X
X
O
(slave mode)
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