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2.7.2 Operation of frequency synthesizer
The following explains how to setup after hardware reset. Table 2.7.1 to 2.7.3 show frequency synthe-
sizer related registers setting examples.
Operation
(1) Cancel the protect register.
(2) Set the frequency synthesizer related registers to generate the 48MHz clock that is necessary
(3) Enable the frequency synthesizer by setting frequency synthesizer control register.
(4) The protect register should be set to write disabled. A 3ms wait is necessary.
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(5) The frequency synthesizer locked status bit should be checked. It is necessary to recheck
(6) Enable USB clock.
(7) After waiting four cycles of the φ or greater, the USB enable bit should be set to "1".
Prescaler
Clock f(X
When the frequency synthesizer prescaler register is set at 255, the prescaler is disabled and f
f(X
). Table 2.7.1 shows some examples of how the frequency synthesizer prescaler register is set.
IN
f
= f(X
PIN
Note: The value of f
Table 2.7.1. Example of setting the frequency synthesizer prescaler register (FSP)
f
PIN
12 MH
1 MH
1 MH
2 MH
2 MH
3 MH
6 MH
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
for the f
.
USB
after a wait of 0.1ms if it is "0" (unlocked).
A minimum delay of 250ns is needed before performing any other USB related registers read/
write operations.
) is prescaled down by the frequency synthesizer prescaler register (FSP) to generate f
IN
) / 2(n+1) n: FSP value
IN
should not be set below 1 MHz.
PIN
FSP Value
Dec (Hex)
255 (FF
)
Z
16
7 (07
)
Z
16
5 (05
)
Z
16
3 (03
)
Z
16
2 (02
)
Z
16
1 (01
)
Z
16
0 (00
)
Z
16
page 124 of 354
fX
(IN)
12.00 MH
Z
16.00 MH
Z
12.00 MH
Z
16.00 MH
Z
12.00 MH
Z
12.00 MH
Z
12.00 MH
Z
2. Frequency synthesizer (PLL)
PIN
PIN
.
=
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