Connecting Low-Speed Memory - Renesas M16C Series User Manual

M30245 Group

4.4.2 Connecting Low-Speed Memory

To connect memory with long access time [ta(A)], either decrease the frequency of BCLK or set a soft-
ware wait. Using the RDY feature allows you to connect memory having the timing that precludes con-
nection though you set software wait.
(1) Using software wait
Set software wait for the external memory areas by using either of bits CS0W through CS3W of the
chip select control register (address 0008
When using the RDY signal, the corresponding CS0W through CS3W bit must be set to "0".
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Bits CS0W through CS3W of the chip select control register correspond to chip select CS0 through
CS3, respectively. If these bits are set to "1", the read bus cycle results in one cycle of BCLK and the
write bus cycle results in two cycles of BCLK; if these bits are set to "0", the read/write cycle results in
two, three, or four cycles of BCLK according to the chip select expansion register setting. When the
corresponding bit of the chip select control register is set to "0", the chip select expansion register
setting becomes valid. When this bit is set to "1", set the corresponding bit of the chip select expansion
register to "00
When reset, the value of the chip select control register and the chip select expansion register is set to
"00
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These control bits do not affect the SFR area and the internal ROM/RAM area.
Figure 4.4.1 shows software wait and bus cycle, and Figure 4.4.3 shows relation of processor mode
and the wait bit (CSiW, CSiEW).
Table 4.4.1. Software waits and bus cycles
Area
SFR
Internal ROM/RAM
External memory
areas
Note 1: When using the RDY signal, set to "0".
Note 2: Set CSEiW bits (i = 0 to 3) after setting the corresponding CSiW bit (i = 0 to 3) of the CSR register
to "0". When CSiW bits are set to "1", CSEiW bits must be returned to "00
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
________
________
".
2
".
CSxW
(Note 2)
Invalid
Invalid
0
0
0
0
1
_______
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) or the chip select expansion register (address 001B
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CSExW
(Note 2) Read
Invalid 2 BCLK cycles
Invalid 1 BCLK cycle
00 2 BCLK cycles
01 3 BCLK cycles
10 4 BCLK cycles
11
00 1 BCLK cycle
4. External Buses
Bus Cycles
Write
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
3 BCLK cycles
4 BCLK cycles
Do not set
2 BCLK cycles
".
2
).
16