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2.10 DMAC Usage
2.10.1 Overview of the DMAC usage
DMAC transfers one data item held in the source address to the destination address every time a transfer
request is generated. The following is an overview of the DMAC usage.
(1) Source address and destination address
Both the register which indicates a source and the register which indicates a destination comprise of
24 bits, so that each can cover a 1M bytes space. After transfer of one bit of data is completed, the
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address in either the source register or the destination register can be incremented. However, both
registers cannot be incremented. The links between the source and destination are as follows:
(a) A fixed address from an arbitrary 1M bytes space
(b) An arbitrary 1M bytes space from a fixed address
(c) A fixed address from another fixed address
([0020
(2) The number of bits of data transferred
The number of bit of data indicated by the transfer counter is transferred. If a 16-bit transfer is se-
lected, up to 128K bytes can be transferred. If an 8-bit transfer is selected, up to 64K bytes can be
transferred. The transfer counter is decremented each time one bit of data is transferred, and a DMA
interrupt request occurs when the transfer counter underflows.
(3) DMA transfer factor
The DMA transfer factor can be selected from the following 31 factors: falling edge/two edges of INT0/
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INT1/INT2 pin, timer A0 interrupt request through timer A4 interrupt request, UART0 transmission/
NACK/SS interface 0 transmission interrupt request, UART0 reception/ACK/SS interface 0 reception
interrupt request, UART1 transmission/NACK/SS interface 1 transmission interrupt request, UART1
reception/ACK/SS interface 1 reception interrupt request, UART2 transmission/NACK interrupt re-
quest, UART2 reception/ACK interrupt request, UART3 transmission/NACK interrupt request, UART3
reception/ACK interrupt request, USB0/USB1/USB2/USB3 function interrupt request, A/D conversion
interrupt request, software trigger, and DMA trigger.
Software trigger is always enabled. When software trigger is selected, DMA transfer is generated by
writing "1" to software DMA interrupt request bit. When other factor is selected, DMA transfer is
generated by generating corresponding interrupt request.
(4) Channel priority
High to low priority: DMA0, DMA1, DMA2, DMA3
(5) Writing to a register
When writing to the source register or the destination register with DMA enabled, the content of the
register with a fixed address will change at the time of writing. Therefore, the user should not write to
a register with a fixed address when the DMA enable bit is set to "1". The contents of the register with
'forward direction' selected, and the transfer counter, are changed when reloaded. A reload occurs
either when the transfer counter underflows, or when the DMA enable bit is re-enabled, after having
been disabled.
The reload register can be written to, as in normal conditions.
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
to 003F
and 0180
to 019F
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2. DMAC
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