Basic Internal And External Bus Cycles - Intel 386 User Manual

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Figure 6-4 shows internal and external bus cycles.
Cycle
State
CLK2
CLKOUT
A25:1, BHE#
BLE#, D/C#
M/IO#
REFRESH#
W/R#
WR#
RD#
ADS#
NA#
READY#
LBA#
BS8#
LOCK#
D15:0
Figure 6-4. Basic Internal and External Bus Cycles
6-12
Idle
Cycle 1 Cycle 2
Nonpipelined Nonpipelined
External Internal
(Write) (Read)
[Late Ready]
T1 T2 T1
Ti
Valid 1 Valid 2
End Cycle 1
Valid 1 Valid 2
Out 1
Idle
Cycle 3
Cycle
Nonpipelined
Internal
(Write)
[Early Ready]
T2 T1 T2 Ti
Valid 3
End Cycle 2 End Cycle 3
Valid 3
In
Out 3
2
Idle
Cycle 4
Cycle
Nonpipelined
External
(Read)
T1 T2
Ti
Valid 4
End Cycle 4
Valid 4
In
4
A2486-03