Port Direction Register (P N Dir); Port Data Latch Register (P N Ltc) - Intel 386 User Manual

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Port DIrection
P n DIR ( n =1–3)
(read/write)
7
PD7 PD6
Bit Bit
Number Mnemonic
7–0 PD7:0
Port Data Latch
P n LTC ( n =1–3)
(read/write)
7
PL7 PL6
Bit Bit
Number Mnemonic
7–0 PL7:0
16-8
PD5 PD4
Pin Direction:
0 = Configures the pin as a complementary output.
1 = Configures the pin as an open-drain output or high-impedance input.
Figure 16-4. Port Direction Register (P n DIR)
PL5 PL4
Port Data Latch:
Writing a value to a PL bit causes that value to be driven onto the
corresponding pin.
For a complementary output, write the desired pin value to its PL bit.
This value is strongly driven onto the pin.
For an open-drain output, a one results in a high-impedance (input) state
at the pin.
For a high-impedance input, write a one to the corresponding PL bit. A
one results in a high-impedance state at the pin, allowing external
hardware to drive it.
Figure 16-5. Port Data Latch Register (P n LTC)
Expanded Addr: F864H, F86CH, F874H
ISA Addr: —
Reset State: FFH
PD3 PD2
Function
Expanded Addr: F862H, F86AH, F872H
ISA Addr: —
Reset State: FFH
PL3 PL2
Function
0
PD1 PD0
0
PL1 PL0