Intel 386 User Manual page 364

Expanded
Register
Address
DMASTS F008H
(read only)
DMACMD2 F01AH
(write only)
DMAMOD1 F00BH
(write only)
DMAMOD2 F01BH
(write only)
DMASRR F009H
(read/write)
DMAMSK F00AH
(write only)
DMAGRPMSK F00FH
(read/write)
DMABSR F018H
(write only)
Table 12-3. DMA Registers (Sheet 2 of 3)
PC/AT*
Address
0008H DMA Status:
Indicates whether a hardware request is pending on
channel 0 and 1. Indicates whether channel 0's or
channel 1's byte count has expired.
— DMA Command 2:
Assigns a bus control requester (DMA channel 0,
DMA channel 1, or external bus master) to the lowest
priority level. Selects the type of sampling for the end-
of-process (EOP#) and the DMA request (DRQ n )
inputs. The DMA can sample these signals
asynchronously or synchronously.
000BH DMA Mode 1:
Determines the data-transfer mode. Enables the
autoinitialize buffer-transfer mode. Determines the
transfer direction (whether the target is the
destination or source for a transfer). Determines
whether the DMA increments or decrements the
target address during a buffer transfer (only if the
DMA is set up to modify the target address; see
DMAMOD2).
— DMA Mode 2:
Selects the data transfer bus cycle option. Specifies
whether the requester and target are in memory or
I/O. Determines whether the DMA modifies the target
and requester addresses. Determines whether the
DMA increments or decrements the requester
address during a buffer transfer (only if the DMA is set
up to modify the requester address).
0009H DMA Software Request:
Write Format
Generates a channel 0 and/or a channel 1 software
request.
Read Format
Indicates whether a software request is pending on
DMA channel 0 or 1.
000AH DMA Individual Channel Mask:
Individually masks (disables) channel 0's and 1's
hardware request input (DREQ0 and DREQ1). This
does not mask software requests.
000FH DMA Group Channel Mask:
Simultaneously masks (disables) both channels'
hardware request inputs (DREQ0 and DREQ1). This
does not mask software requests.
— DMA Bus Size:
Determines the requester and target data bus widths
(8 or 16 bits).
DMA CONTROLLER
Description
12-29