Dma Temporary Buffer Operation For A Read Transfer; Dma Temporary Buffer Operation For A Write Transfer - Intel 386 User Manual

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Figures 12-2 and 12-3 are simple diagrams of how the Temporary Register is filled and emptied
for a Read DMA cycle and a Write DMA cycle.
Filling the Temporary Register
DREQ n DREQ n
#1 #2
Four separate requests each with a read
of the requester. Each byte is stored in
the Temporary Register.
Figure 12-2. DMA Temporary Buffer Operation for a Read Transfer
Filling the Temporary Register
DREQ n
#1
A single request with four separate reads of
the target. Each read stores a byte in the
Temporary Register.
Figure 12-3. DMA Temporary Buffer Operation for A Write Transfer
12-8
DREQ n DREQ n
#3 #4
Emptying the Temporary Register
Write Write Write
#1 #1 #1
Once the Temporary Resister is full, the
DMA does four burst writes to the target
to empty it.
Emptying the Temporary Register
DREQ n DREQ n DREQ n
#2 #3
Once the Temporary Resister is full, the
DMA does a write cycle to transfer the first
byte from the Temporary Register to the
target. On each subsequent request, the
DMA performs a write cycle transferring a
byte from the Temporary Register to the
target. This continues until empty.
Write
#1
A3381-01
#4
A3382-01