Intel 386 User Manual page 365

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Expanded
Register
Address
DMACHR F019H
(write only)
DMAIEN F01CH
(read/write)
DMAIS F019H
(read only)
DMAOVFE F01DH
(read/write)
12-30
Table 12-3. DMA Registers (Sheet 3 of 3)
PC/AT*
Address
— DMA Chaining:
Enables chaining buffer-transfer mode for a specified
channel.
— DMA Interrupt Enable:
Connects the channel transfer complete status
signals to the interrupt request output (DMAINT).
— DMA Interrupt Status:
Indicates which signal generated an interrupt request:
channel 0 transfer complete, channel 1 transfer
complete, channel 0 chaining, or channel 1 chaining
status.
— DMA Overflow Enable:
Included for 8237A compatibility. Controls whether all
26 bits or only the lower 16 bits of the requester and
target addresses are incremented or decremented
during buffer transfers. Controls whether the byte
count is 24 bits or 16 bits.
Description