Csu Registers - Intel 386 User Manual

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Expanded
Register
Address
PINCFG 0F826H
(read/write)
P2CFG 0F822H
(read/write)
CS0ADH 0F402H
CS1ADH 0F40AH
CS2ADH 0F412H
CS3ADH 0F41AH
CS4ADH 0F422H
CS5ADH 0F42AH
CS6ADH 0F432H
UCSADH 0F43AH
(read/write)
CS0ADL 0F400H
CS1ADL 0F408H
CS2ADL 0F410H
CS3ADL 0F418H
CS4ADL 0F420H
CS5ADL 0F428H
CS6ADL 0F430H
UCSADL 0F438H
(read/write)
CS0MSKH 0F406H
CS1MSKH 0F40EH
CS2MSKH 0F416H
CS3MSKH 0F41EH
CS4MSKH 0F426H
CS5MSKH 0F42EH
CS6MSKH 0F436H
UCSMSKH 0F43EH
(read/write)
CS0MSKL 0F404H
CS1MSKL 0F40CH
CS2MSKL 0F414H
CS3MSKL 0F41CH
CS4MSKL 0F424H
CS5MSKL
0F42CH
CS6MSKL 0F434H
UCSMSKL 0F43CH
(read/write)
14-14
Table 14-2. CSU Registers
Pin Configuration:
Connects the CS6:5# signals to package pins.
Port 2 Configuration:
Connects the CS4:0# signals to package pins.
Chip-select High Address:
Defines the upper 10 bits of the chip-select channel address. The
processor uses a chip-select's channel address to determine the starting
location of the channel's active address block.
Chip-select Low Address:
Defines the lower 5 bits of the chip-select channel address. Configures
the channel for memory or I/O addresses, determines whether or not the
channel is activated when the processor is operating in system
management mode, configures the channel's bus size, defines the
minimum number of wait states inserted into the bus cycle, and defines
whether an external READY# is required to terminate the bus cycle.
Chip-select High Mask:
Defines the upper 10 bits of the chip-select channel mask. The processor
uses a chip-select's channel mask to determine the size of the channel's
active address block and if the address block is repeated.
Chip-select Low Mask:
Defines the lower 5 bits of the chip-select channel mask and enables the
channel's output pin.
Description