Intel 386 User Manual page 657

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Table E-1. Instruction Set Summary (Sheet 19 of 19)
Instruction
table register 0 0 0 0 1 1 1 1
SLDT = store local descriptor table
to register/memory 0 0 0 0 1 1 1 1
SMSW = store machine
0 0 0 0 1 1 1 1
status word
STR = store task register
to register/memory 0 0 0 0 1 1 1 1
VERR = verify read access
register/memory 0 0 0 0 1 1 1 1
VERW = verify write 0 0 0 0 1 1 1 1
access
NOTES:
Notes a through c apply to Real Address Mode only:
a. This is a Protected Mode instruction. Attempted execution in Real Mode will result in exception 6
(invalid opcode).
b. Exception 13 fault (general protection) will occur in Real Mode if an operand reference is made that
partially or fully extends beyond the maximum CS, DS, ES, FS, or GS limit, FFFFH. Exception 12 fault
(stack segment limit violation or not present) will occur in Real Mode if an operand reference is made
that partially or fully extends beyond the maximum SS limit.
c. This instruction may be executed in Real Mode, its purpose is primarily to initialize the CPU for
Protected Mode.
Notes d through g apply to Real Address Mode and Protected Virtual Address Mode:
d. The Intel386 SX CPU uses an early-out multiply algorithm. The actual number of clocks depends on
the position of the most significant bit in the operand (multiplier).
Clock counts given are minimum to maximum. To calculate actual clocks use this formula:
Actual Clock = if m < > 0 then max ([log
In this formula, m is the multiplier, and
b = 9 for register to register
b = 12 for memory to register
E-20
Format
0 0 0 0 0 0 0 1 mod 0 0 1 r/m
0 0 0 0 0 0 0 0 mod 0 0 0 r/m
0 0 0 0 0 0 0 1 mod 1 0 0 r/m
0 0 0 0 0 0 0 0 mod 0 0 1 r/m
0 0 0 0 0 0 0 0 mod 1 0 0 r/m
0 0 0 0 0 0 0 0
mod 1 0 1 r/m
2
if m = 0 then 3 + b clocks
Clock Count
Real
Ad-
dress
Mode
or
Virtual
8086
Mode
9*
N/A
2/2*
N/A
N/A
N/A
|m| ], 3) + b clocks:
Notes
Pro- Real Pro-
tected Ad- tected
Virtual dress Virtual
Ad- Mode Ad-
dress or dress
Mode Virtual Mode
8086
Mode
9* b, c h
2/2* a h
2/2* b, c h, l
2/2* a h
10/11* a g, h, j, p
15/16* a g, h, j, p