Rcu Registers; Register Definitions - Intel 386 User Manual

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL

15.4 REGISTER DEFINITIONS

Table 15-2 provides an overview of the registers associated with the RCU. The following sections
provide specific programming information for each register.
Expanded
Register
Address
RFSCIR 0F4A2H
(read/write)
RFSCON 0F4A4H
(read/write)
RFSBAD 0F4A0H
(read/write)
RFSADD 0F4A6H
(read/write)
15-6
Table 15-2. RCU Registers
Refresh Clock Interval:
Determines the processor clock (CLK2/2) count between refresh requests.
Refresh Control:
Enables the refresh control unit. Reading this register also provides the
current value of the interval counter.
Refresh Base Address:
Contains the A25:14 address bits of the refresh address. This establishes
a memory region for refreshing.
Refresh Address:
Contains the A13:1 address bits of the refresh address. The 13-bit address
counter generates these values.
Description