Intel 386 User Manual page 216

Expanded
Register
Address
IRR (master) 0F020H
IRR (slave) 0F0A0H
(read only)
ISR (master) 0F020H
ISR (slave) 0F0A0H
(read only)
POLL (master) 0F020H
0F021H
POLL (slave) 0F0A0H
0F0A1H
(read only)
NOTE: All master 82C59A registers are accessed through two expanded or PC/AT addresses; all the slave
registers are accessed through two other expanded or PC/AT addresses. The order in which you write
or read these addresses along with certain register bit settings determines which register is accessed.
To initialize the 82C59As:
1. Globally disable all maskable interrupts to the core using the CLI instruction.
2. Write to the initialization command words.
You must initialize both the master and the slave (either can be initialized
first).
The 8259A module has a state machine that controls access to the individual registers. Improper
initialization occurs when the following sequences are not followed:
•
To initialize the master, write to its initialization command words in order (ICW1, ICW2,
ICW3, then ICW4).
•
To initialize the slave, write to its initialization command words in order (ICW1, ICW2,
ICW3, then ICW4).
Table 9-2. ICU Registers (Sheet 2 of 2)
PC/AT*
Address
0020H Interrupt Request:
00A0H
Indicates pending interrupt requests.
0020H In-service:
00A0H
Indicates the interrupt requests that are currently being
serviced.
0020H Poll Status Byte:
0021H
Indicates whether any of the devices connected to the 82C59A
00A0H require servicing. If the 82C59A requires servicing, this byte
00A1H indicates the highest-priority pending interrupt.
NOTE: Once the polling bit is set in OCW3, the Poll Status
Byte of a particular 82C59A can be read by doing an access to
any of the four addresses of that 82C59A.
NOTE
INTERRUPT CONTROL UNIT
Function
9-17