Chip-Select Low Mask Registers (Cs N Mskl, Ucsmskl) - Intel 386 User Manual

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Chip-select Low Mask
CS n MSKL ( n = 0–6), UCSMSKL
(read/write)
15
CM5 CM4
7
— —
Bit Bit
Number Mnemonic
15–11 CM5:1
10 CMSMM
9–1 —
0 CSEN
Figure 14-9. Chip-select Low Mask Registers (CS n MSKL, UCSMSKL)
14-20
CM3 CM2
— —
Chip-select Mask Value Lower Bits:
Defines the lower 5 bits of the channel's 15-bit mask. The mask bits
CM5:1 and the address bits CA5:1 form a masked address that is
compared to memory address bits A15:11 or I/O address bits A5:1.
SMM Mask Bit:
0 = The SMM address bit is not masked.
1 = Masks the SMM address bit in the channel's Chip-Select Low
Address register. When the SMM address bit is masked, an address
match activates the chip-select, regardless of whether the processor
is in SMM.
Reserved; for compatibility with future devices, write zeros to these bits.
Chip-select Enable:
0 = Disables the chip-select channel.
1 = Enables the chip-select channel.
Expanded Addr: F404H, F40CH
F414H, F41CH
F424H, F42CH
F434H, F43CH
ISA Addr: —
Reset State: 0000H (CS n MSKL)
FFFFH (UCSMSKL)
CM1 CMSMM
— —
Function
8
— —
0
— CSEN