Interrupt Process – Master Request From Slave Source - Intel 386 User Manual

Is
Yes
request
enabled?
No
Yes
End
Master sends request to CPU. CPU initiates interrupt acknowledge cycle.
Master clears IR2 pending bit and sets IR2 in-service bit.
Slave clears its pending bit, sets its in-service bit, and puts its interrupt
vector number on the bus.
The CPU uses its operating mode and the interrupt vector number to find
the interrupt service routine's address. The CPU processes the interrupt.
Interrupt routine sends an EOI command to the slave, clearing its IR2
in-service bit
An interrupt return instruction is issued, ending the interrupt process.
Figure 9-5. Interrupt Process – Master Request from Slave Source
Master receives IR2 interrupt request.
Master sets its IR2 pending bit.
Is
No
special
mask mode
enabled?
Yes
Is
the
No
IR2 in-service
bit
set?
No
Does
slave have
other
in-service bits
set?
Yes
INTERRUPT CONTROL UNIT
Is master
No
operating in
special-fully
nested
mode?
Yes
Is
request
No
equal or higher
than any set
in-service
bits?
Yes
No Interrupt routine sends an
EOI command to the master,
clearing its IR2 in-service bit.
(operating in
fully nested
mode)
Is
request
higher level
than any set
in-service
bits?
Yes
A2429-02
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