Interrupt Control Unit Configuration - Intel 386 User Manual

IR0
8259A
Master
IR1
IR2
INT
INTR
IR3
(to
core)
INTCFG.5
IR4
IR5
IR6
CAS2:0
IR7
IR0
INT
8259A
Slave
IR1
IR2
IR3
INTCFG.4
IR4
IR5
CAS2:0
INTCFG.2
IR6
IR7
3
† Alternate pin signals are in parentheses
Heavier lines indicate multiple signals.
Figure 9-1. Interrupt Control Unit Configuration
OUT0 (TCU)
P3CFG.2
0
V
SS
1
To/From I/O Port 3
INTCFG.6
0 SIOINT1
1
OUT1(TCU)
0
SIOINT0
1
P3CFG.3
V
0
SS
1
P3CFG.4
To/From I/O Port 3
0 V
SS
1
To/From I/O Port 3
P3CFG.5
0 V
SS
1
To/From I/O Port 3
INTCFG.0
V
0
SS
1
INTCFG.1
0 SSIOINT
1
OUT1(TCU)
OUT2(TCU)
0
1
0
V
1
0
SS
1
INTCFG.3
V
0
SS
1
WDTOUT#
INTCFG.7
0
V
SS
1
A18:16
INTERRUPT CONTROL UNIT
P3CFG.2
1
0
MCR1.3
SIOINT1
1
INTCFG.6
1
P3CFG.1
0
1
0 P3.1
0
MCR0.3
SIOINT0
1
INTCFG.5
1
0
1
0
OUT0(TCU)
P3.0
P3CFG.3
1
0
P3CFG.4
1
0
P3CFG.5
1
0
To TCU
To TCU
DMAINT
To TCU
To TCU
INT0
(P3.2)†
INT8
TMROUT1
(P3.1)
P3GFG.0
INT9
TMROUT0
(P3.0)
0
INT1
(P3.3)
INT2
(P3.4)
INT3
(P3.5)
INT4
(TMRCLK0)
INT5
(TMRGATE0)
INT6
(TMRCLK1)
INT7
(TMRGATE1)
CAS2:0
(A18:16)
A2522-03
9-3