Intcfg; D.31 Intcfg - Intel 386 User Manual

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL

D.31 INTCFG

Interrupt Configuration

INTCFG

(read/write)
7
CE IR3
Bit Bit
Number Mnemonic
7 CE
6 IR3
5 IR4
4 SWAP
3 IR6
2 IR5/IR4
1 IR1
0 IR0
D-34
IR4 SWAP
Cascade Enable:
0 = Disables the cascade signals CAS2:0 from appearing on the A18:16
address lines during interrupt acknowledge cycles.
1 = Enables the cascade signals CAS2:0, providing access to external
slave 82C59A devices. The cascade signals are used to address
specific slaves. If enabled, slave IDs appear on the A18:16 address
lines during interrupt acknowledge cycles, but are high during idle
cycles.
Internal Master IR3 Connection:
See Table 5-1 on page 5-8 for all the IR3 configuration options.
Internal Master IR4 Connection:
See Table 5-2 on page 5-8 for all the IR4 configuration options.
INT6/DMAINT Connection:
0 = Connects DMAINT to the slave IR4. Connects INT6 to the slave IR5.
1 = Connects the INT6 pin to the slave IR4. Connects DMAINT to the slave
IR5.
Internal Slave IR6 Connection:
0 = Connects V to the slave IR6 signal.
SS
1 = Connects the INT7 pin to the slave IR6 signal.
Internal Slave IR4 or IR5 Connection:
These depend on whether INTCFG.4 is set or clear.
0 = Connects V to the slave IR5 signal.
SS
1 = Connects either the INT6 pin or DMAINT to the slave IR5 signal.
Internal Slave IR1 Connection:
0 = Connects the SSIO interrupt signal (SSIOINT) to the slave IR1 signal.
1 = Connects the INT5 pin to the slave IR1 signal.
Internal Slave IR0 Connection:
0 = Connects V to the slave IR0 signal.
SS
1 = Connects the INT4 pin to the slave IR0 signal.
Expanded Addr: F832H
ISA Addr: —
Reset State: 00H
IR6 IR5/IR4
Function
0
IR1 IR0